View IDT77V011_1527661.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1 of 43 march 15, 2001 ? 2 0 0 1 i n t e g r a t ed d e v i c e t e c hn o lo g y , i n c . dsc 4308/8 data path interface (dpi) to utopia level 2 translation device single chip interface between multiple utopia phys and a single data path interface (dpi). ideal for xdsl dslam and 25mbps switching applications. supports atm forum utopia level 2 interface in both 8-bit and 16-bit modes. supports utopia level 2 cell level handshake. supports up to 31 phys on the utopia level 2 interface. supports either 4-bit or 8-bit dpi interf ace. supports cell sizes from 52 to 56 bytes on the dpi interf ace. supports dpi operation up to 50mhz. either utility bus or parallel manager management interface for configuring and reading status of phy registers. in-stream? (in-band) programming for configuration of device and management interface communications. tag routing for flexibility in routing cells. single +3.3v 0.3v power supply required. inputs are +5.0v tolerant.

the IDT77V011provides the interface translation between a 4 or 8-bit data path interface (dpi) and an 8 or 16-bit utopia level 2 interface. dpi offers a reduced device pin count and gives the idt77v400 switching memory a high degree of port configuration flexibility. by providing a smooth translation to the utopia level 2 multi-phy interface, the IDT77V011 offers the opportunity to connect up to 31 phy ports to a single 155mbps port of the idt77v 400 switching memory. the IDT77V011 can also provide both transmit and receive tag routing, with each direction being individually programmed. in the receive direction up to four bytes can be added to the cell. in the transmit direction up to four bytes can be removed from the cell. this makes the IDT77V011, when combined with the idt77v400, an ideal component for dslam and 25mbps applications where the user would like to implement oc-3 bandwidth of a single idt77v400 port to a number of lower bandwidth ports. the 77v011 utilizes in-stream? programming for its device configu- ration options. the cells are received on the dpi trans mit interface, iden- tified and sent to the internal cell interpre ter for decoding and execution. in-stream? programming cells are transmitted based on a round-robin scheduler, which provides equal prior ity for each of the subports and the cell generator. this methodology is also used to communicate and configure the phys that are connected to the IDT77V011. other features include an eeprom that holds information for initial- ization and discovery/identify cells, and a management interface to access the phy devices.

figure 1 typical idt77011 adsl dslam application with the idtv400 switching memory adsl phy adsl phy adsl phy IDT77V011 dpi 4/8-bit utopia 2 8/16-bit idt77v400 switching memory management bus 5348drw01 . . . id t7 7v 01 1
2 of 43 march 15, 2001 IDT77V011

1. all power pins must be connected to a 3.3v 0.3v power supply. 2. all gnd pins must be connected to ground supply. 3. this text does not indicate orientat ion of the actual part-marking. dpi transmit interface eeprom interface utopia ii transmit interface dpi receive interface utopia ii receive interface management interface tag & port address removal cell receiver cell generator tag & port address adder 5348drw02 index txdata[11] txdata[7] txdata[10] txdata[9] txdata[8] txdata[6] IDT77V011 pqfp top view 3 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 17 18 19 20 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 21 txref gnd gnd 4 8 4 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 3 9 3 8 3 7 4 9 5 0 5 1 5 2 5 3 5 4 5 5 5 6 5 7 5 8 5 9 6 0 6 1 6 2 6 3 6 4 6 5 6 6 6 7 6 8 6 9 7 0 7 1 7 2 v c c d r x d a t a [ 3 ] d r x d a t a [ 4 ] d r x d a t a [ 5 ] d r x d a t a [ 6 ] d r x d a t a [ 7 ] v c c g n d s y s c l k s y s r s t e e d i n e e d o u t e e c s e e c l k g n d c t r l _ b c t r l _ a m b u s [ 1 1 ] v c c m g m t [ 4 ] g n d g n d vcc txdata[5] vcc txdata[4] txdata[3] txdata[2] txdata[1] txdata[0] gnd vcc dtxdata[0] dtxdata[1] dtxfrm gnd dtxclk vcc drxclk drxfrm drxdata[0] drxdata[1] drxdata[2] gnd 101 100 99 98 97 96 95 94 93 108 107 106 105 104 103 102 92 91 90 89 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 88 vcc rxdata[14] rxdata[13] rxdata[12] rxdata[11] rxdata[10] rxdata[9] vcc gnd rxdata[7] rxdata[6] rxdata[4] rxdata[3] rxdata[2] rxdata[1] rxdata[0] vcc gnd mdata[7] mdata[6] mdata[5] mdata[4] mdata[3] mdata[2] mdata[1] mdata[0] gnd mgmt[5] mgmt[1] mgmt[2] mgmt[3] phyrst 1 3 3 1 3 4 1 3 5 1 3 6 1 3 7 1 3 8 1 3 9 1 4 0 1 4 1 1 4 2 1 4 3 1 4 4 1 3 2 1 3 1 1 3 0 1 2 9 1 2 8 1 2 7 1 2 6 1 2 5 1 2 4 1 2 3 1 2 2 1 2 1 1 2 0 1 1 9 1 1 8 1 1 7 1 1 6 1 1 5 1 1 4 1 1 3 1 1 2 1 1 1 1 1 0 1 0 9 r e f c l k v c c r x d a t a [ 1 5 ] t e n b r x a d d r [ 4 ] r c l a v r s o c r x a d d r [ 3 ] g n d v c c r x l e d r x a d d r [ 2 ] r x a d d r [ 1 ] r x a d d r [ 0 ] t c l a v r e n b g n d r c l k g n d t c l k t x a d d r [ 0 ] t x a d d r [ 1 ] t x a d d r [ 2 ] t x a d d r [ 3 ] t x a d d r [ 4 ] t x p r t y t x l e d v c c g n d t s o c 5348drw03 vcc rxdata[8] dtxdata[2] dtxdata[3] dtxdata[4] dtxdata[5] dtxdata[6] dtxdata[7] v c c m b u s [ 1 0 ] m b u s [ 9 ] m b u s [ 8 ] m b u s [ 7 ] m b u s [ 6 ] m b u s [ 5 ] m b u s [ 4 ] m b u s [ 3 ] m b u s [ 2 ] m b u s [ 1 ] m b u s [ 0 ] b m o d e p h y i n t rxdata[5] v c c t x d a t a [ 1 5 ] t x d a t a [ 1 4 ] t x d a t a [ 1 3 ] t x d a t a [ 1 2 ] g n d
3 of 43 march 15, 2001 IDT77V011

dtxdata [0] 19 i normal 4-bit or 8-bit input data bus used to transfer data from a dpi device. when in 4-bit mode use dtxdata [3:0] . dtxdata [1] 20 i normal 4-bit or 8-bit input data bus used to transfer data from a dpi device. when in 4-bit mode use dtxdata [3:0] . dtxdata [2] 21 i normal 4-bit or 8-bit input data bus used to transfer data from a dpi device. when in 4-bit mode use dtxdata [3:0] . dtxdata [3] 22 i normal 4-bit or 8-bit input data bus used to transfer data from a dpi device. when in 4-bit mode use dtxdata [3:0] . dtxdata [4] 23 i normal 4-bit or 8-bit input data bus used to transfer data from a dpi device. when in 4-bit mode use dtxdata [3:0] . dtxdata [5] 24 i normal 4-bit or 8-bit input data bus used to transfer data from a dpi device. when in 4-bit mode use dtxdata [3:0] . dtxdata [6] 25 i normal 4-bit or 8-bit input data bus used to transfer data from a dpi device. when in 4-bit mode use dtxdata [3:0] . dtxdata [7] 26 i normal 4-bit or 8-bit input data bus used to transfer data from a dpi device. when in 4-bit mode use dtxdata [3:0] . dtxfrm 27 i normal dpi transmit start of frame marker. dtxclk 29 o normal transmit dpi clock. drxdata [0] 33 o normal 4-bit or 8-bit output data bus used to transfer data to a dpi device. when in 4-bit mode use drxdata [3:0]. drxdata [1] 34 o normal 4-bit or 8-bit output data bus used to transfer data to a dpi device. when in 4-bit mode use drxdata [3:0]. drxdata [2] 35 o normal 4-bit or 8-bit output data bus used to transfer data to a dpi device. when in 4-bit mode use drxdata [3:0]. drxdata [3] 38 o normal 4-bit or 8-bit output data bus used to transfer data to a dpi device. when in 4-bit mode use drxdata [3:0]. drxdata [4] 39 o normal 4-bit or 8-bit output data bus used to transfer data to a dpi device. when in 4-bit mode use drxdata [3:0]. drxdata [5] 40 o normal 4-bit or 8-bit output data bus used to transfer data to a dpi device. when in 4-bit mode use drxdata [3:0]. drxdata [6] 41 o normal 4-bit or 8-bit output data bus used to transfer data to a dpi device. when in 4-bit mode use drxdata [3:0]. drxdata [7] 42 o normal 4-bit or 8-bit output data bus used to transfer data to a dpi device. when in 4-bit mode use drxdata [3:0]. drxfrm 32 o normal dpi receive start of frame marker. drxclk 31 i/o normal receive dpi clock. rxdata [0] 91 i normal 8-bit or 16-bit utopia 2 input data bus used to transfer data f rom a phy device. w hen in 8-bit mode use rxdata [7:0]. rxdata [1] 92 i normal 8-bit or 16-bit utopia 2 input data bus used to transfer data f rom a phy device. w hen in 8-bit mode use rxdata [7:0]. rxdata [2] 93 i normal 8-bit or 16-bit utopia 2 input data bus used to transfer data f rom a phy device. w hen in 8-bit mode use rxdata [7:0]. rxdata [3] 94 i normal 8-bit or 16-bit utopia 2 input data bus used to transfer data f rom a phy device. w hen in 8-bit mode use rxdata [7:0]. rxdata [4] 95 i normal 8-bit or 16-bit utopia 2 input data bus used to transfer data f rom a phy device. w hen in 8-bit mode use rxdata [7:0]. rxdata [5] 96 i normal 8-bit or 16-bit utopia 2 input data bus used to transfer data f rom a phy device. w hen in 8-bit mode use rxdata [7:0]. rxdata [6] 97 i normal 8-bit or 16-bit utopia 2 input data bus used to transfer data f rom a phy device. w hen in 8-bit mode use rxdata [7:0]. rxdata [7] 98 i normal 8-bit or 16-bit utopia 2 input data bus used to transfer data f rom a phy device. w hen in 8-bit mode use rxdata [7:0]. rxdata [8] 101 i normal 8-bit or 16-bit utopia 2 input data bus used to transfer data f rom a phy device. w hen in 8-bit mode use rxdata [7:0]. rxdata [9] 102 i normal 8-bit or 16-bit utopia 2 input data bus used to transfer data f rom a phy device. w hen in 8-bit mode use rxdata [7:0].
4 of 43 march 15, 2001 IDT77V011 rxdata [10] 103 i normal 8-bit or 16-bit utopia 2 input data bus used to transfer data f rom a phy device. w hen in 8-bit mode use rxdata [7:0]. rxdata [11] 104 i normal 8-bit or 16-bit utopia 2 input data bus used to transfer data f rom a phy device. w hen in 8-bit mode use rxdata [7:0]. rxdata [12] 105 i normal 8-bit or 16-bit utopia 2 input data bus used to transfer data f rom a phy device. w hen in 8-bit mode use rxdata [7:0]. rxdata [13] 106 i normal 8-bit or 16-bit utopia 2 input data bus used to transfer data f rom a phy device. w hen in 8-bit mode use rxdata [7:0]. rxdata [14] 107 i normal 8-bit or 16-bit utopia 2 input data bus used to transfer data f rom a phy device. w hen in 8-bit mode use rxdata [7:0]. rxdata [15] 110 i normal 8-bit or 16-bit utopia 2 input data bus used to transfer data f rom a phy device. w hen in 8-bit mode use rxdata [7:0]. rsoc 111 i normal utopia 2 receive start of cell marker. rclav 112 i normal utopia 2 receive cell available. renb 121 o normal utopia 2 receive enable. rxaddr [0] 120 o normal utopia 2 receive address bus. rxaddr [1] 119 o normal utopia 2 receive address bus. rxaddr [2] 118 o normal utopia 2 receive address bus. rxaddr [3] 117 o normal utopia 2 receive address bus. rxaddr [4] 116 o normal utopia 2 receive address bus. rxled 115 o normal utopia 2 receive led. rclk 122 o normal utopia 2 receive clock. txdata [0] 15 o normal 8-bit or 16-bit utopia 2 output data bus used to transfer data to a phy device. when in 8-bit mode use txdata [7:0]. txdata [1] 14 o normal 8-bit or 16-bit utopia 2 output data bus used to transfer data to a phy device. when in 8-bit mode use txdata [7:0]. txdata [2] 13 o normal 8-bit or 16-bit utopia 2 output data bus used to transfer data to a phy device. when in 8-bit mode use txdata [7:0]. txdata [3] 12 o normal 8-bit or 16-bit utopia 2 output data bus used to transfer data to a phy device. when in 8-bit mode use txdata [7:0]. txdata [4] 11 o normal 8-bit or 16-bit utopia 2 output data bus used to transfer data to a phy device. when in 8-bit mode use txdata [7:0]. txdata [5] 8 o normal 8-bit or 16-bit utopia 2 output data bus used to transfer data to a phy device. when in 8-bit mode use txdata [7:0]. txdata [6] 7 o normal 8-bit or 16-bit utopia 2 output data bus used to transfer data to a phy device. when in 8-bit mode use txdata [7:0]. txdata [7] 6 o normal 8-bit or 16-bit utopia 2 output data bus used to transfer data to a phy device. when in 8-bit mode use txdata [7:0]. txdata [8] 5 o normal 8-bit or 16-bit utopia 2 output data bus used to transfer data to a phy device. when in 8-bit mode use txdata [7:0]. txdata [9] 4 o normal 8-bit or 16-bit utopia 2 output data bus used to transfer data to a phy device. when in 8-bit mode use txdata [7:0]. txdata [10] 3 o normal 8-bit or 16-bit utopia 2 output data bus used to transfer data to a phy device. when in 8-bit mode use txdata [7:0].

5 of 43 march 15, 2001 IDT77V011 txdata [11] 2 o normal 8-bit or 16-bit utopia 2 output data bus used to transfer data to a phy device. when in 8-bit mode use txdata [7:0]. txdata [12] 143 o normal 8-bit or 16-bit utopia 2 output data bus used to transfer data to a phy device. when in 8-bit mode use txdata [7:0]. txdata [13] 142 o normal 8-bit or 16-bit utopia 2 output data bus used to transfer data to a phy device. when in 8-bit mode use txdata [7:0]. txdata [14] 141 o normal 8-bit or 16-bit utopia 2 output data bus used to transfer data to a phy device. when in 8-bit mode use txdata [7:0]. txdata [15] 140 o normal 8-bit or 16-bit utopia 2 output data bus used to transfer data to a phy device. when in 8-bit mode use txdata [7:0]. tsoc 134 o normal utopia 2 transmit start of cell marker. tclav 126 i normal utopia 2 transmit cell available. tenb 138 o normal utopia 2 transmit enable. txaddr[0] 129 o normal utopia 2 transmit address bus [lsb]. i reset subport byte location. indicates what byte the tx and rx s ubport address is located in [lsb]. txaddr[1] 130 o normal utopia 2 transmit address bus [lsb+1]. i reset subport byte location. indicates what byte the tx and rx s ubport address is located in [lsb+1]. txaddr[2] 131 o normal utopia 2 transmit address bus [lsb+2]. i reset subport byte location. indicates what byte the tx and rx s ubport address is located in [msb]. txaddr[3] 132 o normal utopia 2 transmit address bus [lsb+3]. i reset initialize from eeprom. selects whether five bytes of eeprom are to be written to in-stream ? cell header and in-stream ? subport. "0" do not write five byte value, "1" write five byte value from eeprom. txaddr[4] 133 o normal utopia 2 transmit address bus [msb]. txled 137 o normal utopia 2 transmit led. tclk 128 o normal utopia 2 transmit clock. txprty 139 o normal parity for dtxdata [15:0]. refclk 125 i normal 8 khz reference clock used to generate txref. txref 16 o normal 8khz reference clock used by phy. eeclk 50 o normal eeprom clock. eecs 49 o normal eeprom chip select. eedin 47 i normal serial input from the eeprom. eedout 48 o normal serial output to the eeprom. bmode 70 i normal bus mode. selects motorola or intel bus m ode. "0" selects motorola, "1" selects intel. mbus[0] 67 o utopia 2 address bus. upper 64 bytes used for 32 address pointers describing phy's. utility bus utility bus phy chip select (cs[1]). i reset txsize[0] - number of bytes to remove from cell in transmit direction (lsb). mbus[1] 66 o utopia 2 address bus. upper 64 bytes used for 32 address pointers describing phy's. utility bus utility bus phy chip select (cs[2]). i reset txsize[1] - number of bytes to remove from cell in transmit direction (lsb + 1).

6 of 43 march 15, 2001 IDT77V011 mbus[2] 65 o utopia 2 address bus. upper 64 bytes used for 32 address pointers describing phy's. utility bus utility bus phy chip select (cs[3]). i reset txsize[2] - number of bytes to remove from cell in transmit direction (msb). mbus[3] 64 o utopia 2 address bus. upper 64 bytes used for 32 address pointers describing phy's. utility bus utility bus phy chip select (cs[4]). i reset txloc - location of tx tag in cell. "0" tag located at beginning of cell, "1" tag located at end of cell. mbus[4] 63 o utopia 2 address bus. upper 64 bytes used for 32 address pointers describing phy's. utility bus utility bus phy chip select (cs[5]). i reset txhec - add hec placeholder. "0" do not add placeholder, "1" add plac ehol der. mbus[5] 61 o utopia 2 address bus. upper 64 bytes used for 32 address pointers describing phy's. utility bus utility bus phy chip select (cs[6]). i reset rxsize[0] - number of bytes to add to cell in the receive direction (lsb). mbus[6] 60 o utopia 2 address bus. upper 64 bytes used for 32 address pointers describing phy's. utility bus utility bus phy chip select (cs[7]). i reset rxsize[1] - number of bytes to add to cell in the receive direction (lsb + 1). mbus[7] 59 o utopia 2 address bus. upper 64 bytes used for 32 address pointers describing phy's. utility bus utility bus phy chip select (cs[8]). i reset rxsize[2] - number of bytes to add to cell in the receive direction (msb). mbus[8] 58 o utopia 2 address bus. upper 64 bytes used for 32 address pointers describing phy's. utility bus utility bus phy chip select (cs[9]). i reset rxloc - location of tag in cell in the receive direction. rxloc = "0" tag located at beginning of cell, txloc = "1" tag located at end of cell. mbus[9] 57 o utopia 2 address bus (lsb+9). utility bus utility bus phy chip select (cs[10]). i reset rxhec - remove hec from cell. "0" do not remove hec, "1" remove hec. mbus[10] 56 o utopia 2 address bus. upper 64 bytes used for 32 address pointers describing phy's. utility bus utility bus phy chip select (cs[11]). i reset dpi bus size. indicates whether dpi transmit and receive bus is 4-bits or 8-bits wide. "0" 4-bit dpi bus, "1" 8-bit dpi bus. mbus[11] 55 o utopia 2 address bus. upper 64 bytes used for 32 address pointers describing phy's. utility bus utility bus phy chip select (cs[12]). i reset utopia bus size. indicates whether the utopia transmit and receive data bus is 8-bits or 16-bits wide. "0" 8-bit utopia bus, "1" 16-bit utopia bus. mdata[0] 81 i/o utopia 2 management interface data bus [lsb]. utility bus utility bus address and data bus [lsb]. mdata[1] 82 i/o utopia 2 management interface data bus [lsb+1]. utility bus utility bus address and data bus [lsb+1]. mdata[2] 83 i/o utopia 2 management interface data bus [lsb+2]. utility bus utility bus address and data bus [lsb+2].

7 of 43 march 15, 2001 IDT77V011 mdata[3] 84 i/o utopia 2 management interface data bus [lsb+3]. utility bus utility bus address and data bus [lsb+3]. mdata[4] 85 i/o utopia 2 management interface data bus [lsb+4]. utility bus utility bus address and data bus [lsb+4]. mdata[5] 86 i/o utopia 2 management interface data bus [lsb+5]. utility bus utility bus address and data bus [lsb+5]. mdata[6] 87 i/o utopia 2 management interface data bus [lsb+6]. utility bus utility bus address and data bus [lsb+6]. mdata[7] 88 i/o utopia 2 management interface data bus [msb]. utility bus utility bus address and data bus [msb]. mgmt[1] 77 o utopia 2 validates read or write operation on m anage ment interface (sel). utility bus utility bus phy chip select (cs[0]). mgmt[2] 76 o utopia ii management interface read or data s trobe (rd/ds). utility bus utility bus read (rd). i reset mmode - selects what type of management m ode interface to use. "0" selects utility bus style, "1" selects utopia 2 style. mgmt[3] 75 o utopia 2 management interface write or read/write (wr/rw). utility bus utility bus write (wr). i reset mgmt[3] - selects clock direction for drxclk. "0" drxclk is an ou tput, "1" drxclk is an input. mgmt[4] 69 i utopia 2 management interface ready or data acknowledge (rdy/dtack). utility bus no functionality. mgmt[5] 78 o utopia ii no functionality. utility bus utility bus address latch enable (ale). phyrst 74 o normal phy reset. resets the phy device attached to the 77v 011. phyint 71 i normal phy interrupt. phy layer interrupt with open drain active low output. sysrst 46 i normal system reset. resets the 77v011 and the phy device(s) attac hed to it. sysclk 45 i normal system clock. ctrl_a 53 o normal control a for system engineering usage. this signal is low after reset. ctrl_b 52 o normal control b for system engineering usage. this signal is low after reset. vcc 1,10,18,30, 37,43,54,68, 73,80,90,100, 109,114,124, 136 power normal 3.3v power supply pins. gnd 9,17,28,36, 44,51,62,72, 79,89,99,108, 113,123,127, 135,144 ground normal ground pins.

8 of 43 march 15, 2001 IDT77V011

v cc 3.3v digital supply voltage gnd-0.3 3.6 v vi n digital input voltage gnd-0.3 5.50 v v out digital output voltage gnd-0.3 vcc v gnd digital ground voltage 0 0 v i out output current ? 12.0 ma t stg storage temperature -55 140 c
v cc 3.3v digital supply voltage 3.0 3.6 v v in ttl input voltage gnd 5.50 v t a industrial operating temperature -40 +85 c titr input ttl rise time ? 2ns titf input ttl fall time ? 2ns v ih ttl input high voltage 2.0 ? v v il ttl input low voltage ? 0.8 v
|i li | input leakage current v cc = 3.3v, v in = 0v to v cc 10 10 a |i lo | output leakage current v out = 0v to v cc 10 10 a v oh ttl output high voltage i oh = -4ma 2.4 ? v v ol ttl output low voltage i ol = +4ma ? 0.4 v icc power supply current 155.52 mbps ? 110 ma
c in input capacitance all inputs ? 4 ? pf c out output capacitance all outputs ? 6 ? pf c bid bi-directional capacitance all bi-directional pins ? 10 ? pf
9 of 43 march 15, 2001 IDT77V011 !
" !
" !
" !
" the 77v011 uses a utopia level 2 interface to receive and transmit atm cells to and from the phy device. it is a master utopia interface and can operate with either an 8-bit or 16-bit data bus. cell level hand- shake is used to transfer cells over the utopia interface, byte level handshake is not supported. the data path interface (dpi) can be used with a 4-bit or 8-bit data bus. the dpi receive interface can be programmed to operate with the clock as an input or output to accommodate either the idt switchstar or a normal mode dpi device. the eeprom holds information for initialization and di scovery/iden- tify cells. the eeprom is an optional device and does not need to be implemented. the management interface contains the control pins used to access the internal phy registers during normal operation, and to program the pin configurable registers at reset. the misc. interface contains two output test pins that can be controlled through the registers. figure 2 77v011 interfaces ! "# 4-bit dpi 8-bit utopia 2 4-bit dpi 16-bit utopia 2 8-bit dpi 8-bit utopia 2 8-bit dpi 16-bit utopia 2 drxclk dtxclk sysclk sysclk sysclk sysclk rclk tclk sysclk/2 sysclk/4 sysclk sysclk/2 table 1 clock relationship and f requency drxfrm drxclk drxdata[7:0] dtxfrm dtxclk dtxdata[7:0] rsoc rclk rxdata[15:0] renb rclav tsoc tclk txdata[15:0] tenb tclav eecs eeclk bmode mgmt[1] mgmt[4] 5348drw04 IDT77V011 eeout txref dpi receive interface dpi transmit interface eein serial eeprom interface sysrst sysclk refclk system interface rxaddr[4:0] txaddr[4:0] mbus[11:0] mdata[7:0] phyint mgmt[2] mgmt[3] phyrst managment interface utopia transmit interface utopia receive interface txprty mgmt[5] cntrl_a cntrl_b misc. interface
10 of 43 march 15, 2001 IDT77V011

all clocks within the 77v011 are derived from the system clock (sysclk). the frequency at which each output clock operates is dependent on the sysclk frequency and on the width of the dpi and utopia 2 interfaces. see clock relationship table for the relationship between sysclk and the output clocks. when drxclk is configured as an input it is totally asynchronous to sysclk. the drxclk clock domain within the 77v011 will run at the same frequency as the drxclk pin. # # # # " $ " $ " $ " $

! ! ! ! " " " "

the 77v011 offers a fully compliant utopia level 2 receive inter- face, as specified by the utopia level 2 specification. the interface is a utopia master and will operate with either an 8-bit or 16-bit input data bus (rxdata[15:0]). utopia cell level handshake is used to receive atm cells from the phy device. the other signals associated with this interface are receive start of cell (rsoc), receive enable (renb ), receive cell available (rclav), receive clock (rclk), receive address bus (rxaddr[4:0]) and receive led (rxled). the rxaddr[4:0] bus is fully utopia level 2 compliant and oper- ates according to the mphy cell-level handshake with one rclav, as described in the utopia level 2 specification. rclk is a continuous clock, whose relationship to sysclk is defined in the clock relationship and frequency table. rxled indicates if there is activity on the rxdata[15:0] bus. this signal asserts high when a cell is transferred over the bus and will stay high for 2 22 rclk cycles. at 40mhz this is approximately 0.1seconds. utopia transmit and receive bus size is selected at reset with the mbus[11] signal. setting mbus[11] to a zero will select a 8-bit bus, while setting mbus[11] to a one will select a 16-bit bus. the value of mbus[11], at reset, is stored in the utopia 2 size bit of the mode select register. see the utopia 2 receive register table for register description. polling on the utopia 2 receive bus is done in a round robin fashion. the max subports field of the configuration 2 register deter- mines the upper boundary of the polled addresses. the default value of the max subports field is 0x1e, which is also the maximum valid phy address. the user should not program a value of 0x1f, as this is defined as a null phy port by the utopia 2 specification. when there is no cell transfer in progress, no phy port is selected, the polling sequence is to output the null phy subport address (0x1f) on one rclk cycle and then output a valid phy s ubport address on the next rclk cycle. this sequence is repeated starting at phy port address 0x00 and ending at the value specified in max subports field. the 77v011 will wrap back to address 0x00 once it has polled the max subports address. a phy device is selected when a phy responds to its subport address by asserting rclav high. renb will assert on the same rclk cycle that rclav is asserted, assuming there is no valid cell transfer in progress. the 77v011 will resume polling starting with the next sequential subport address once the cell transfer to a selected phy port begins. when a phy port responds with a high rclav during a cell transfer the 77v011 will continue to place the responding phy subport address on the rxaddr[4:0] bus until the current cell transfer has ended and the responding phy is given control of the bus. for example, if phy 0x03 responds by asserting rclav while phy 0x08 is still transferring a cell, then the 77v011 will cont inue to place phy s ubport address 0x03 on the rxaddr[4:0] bus. this will continue until phy 0x08 has finished its cell transfer and phy 0x03 is given control of the receive bus. polling will then resume with phy subport address 0x04. a variance in the polling state machine may occur when drxclk is an input to the 77v011 and the frequency of drxclk is low enough to cause the utopia receive bus to interrupt the cell transfer. the inter- ruption will be indicated by renb de-asserting high during the cell transfer. data transfer will resume, where it left off, when renb re- asserts low. in order to resume the current cell transfer the same phy subport address is placed on the rxaddr[4:0] bus one rclk cycle before renb is re-asserted low. each time a cell transfer is interrupted the polling sequence is interrupted in this manner, which may happen frequently if drxclk is much slower than sysclk. for example if phy port 0x03 is given control of the bus to transfer a cell. once phy port 0x03 takes control of the bus the 77v011 begins its polling sequence starting with phy port 0x04. in the middle of the cell transfer data is halted by renb de-asserting high, due to the dpi interface. at this time data transfer is halted while 77v011 is polling phy port 0x08. after some period of time the dpi interface starts to transfer the remainder of the cell. the 77v011 puts the phy subport address 0x03 on the rxaddr[4:0] bus and then asserts renb low on the next rclk cycle. data transfer resumes where it had left off and the 77v011 starts polling the phy ports starting at phy subport address 0x09. in 8-bit utopia mode there is a maximum one clock cycle delay between back to back cells when a tag is not being used, and a maximum seven clock cycle delay when a four byte tag is used. in 16- bit mode there is a maximum one clock cycle delay between back to back cells when a tag is not being used, and a maximum five clock cycle delay when a four byte tag is used. # # # # " " " " $ $ $ $
"
"
"
"

the 77v011 offers a fully compliant utopia level 2 transmit inter- face, as specified by the utopia level 2 specificati on. this is a master utopia interface that uses utopia cell level handshake to transmit atm cells to the phy device. it will operate with either a 8-bit or 16-bit output data bus (txdata[15:0]). other signals associated with this interface are transmit start of cell (tsoc), transmit enable (tenb ), transmit clock (tclk), transmit cell available (tclav), transmit reference clock (txref), reference clock (refclk), transmit parity (txprty), transmit address bus (txaddr[4:0]) and transmit led (txled). tclk is a continuous clock, whose relationship is defined in the clock relationship and frequency table.
11 of 43 march 15, 2001 IDT77V011 figure 3 polling seq uence with no cell transfer in progress figure 4 polling sequence with cell transfer in progress $% $% ! & ! ' $% ( ' mode select 8006 2 utopia 2 size 0 - 1 defined by pin selects the size of the utopia 2 transmit and receive data bus. "0" 8-bit utopia 2 transmit and receive data bus, "1" 16-bit utopia 2 transmit and receive data bus. table 2 utopia 2 receive register table 1 rclk (output) rclav (input) renb (output) rsoc (input) rxdata[7:0] (input) 2 . 1c 1f 1b 1f 1 1f rxaddr[4:0] (output) 1f 21f 3 1f 1f 123 1a 1b 1c 1e 5348drw 0 1 rclk (output) rclav (input) renb (output) 5348drw0 rsoc (input) rxdata[7:0] (input) 71f 1f 1 1f rxaddr[4:0] (output) 8 6 1f 6 1f 1f 14 5 6 6 7 5 53 52 51 50 49 48 47 6 5 2 output on the txaddr[4:0] bus until another cell enters the 77v011 on the transmit dpi interface. when a cell is detected on the transmit dpi interface and a cell transfer is in progress on the transmit utopia 2 interface, the subport is extracted and output on the txaddr[4:0] bus, interleaved with the null phy subport address, to query the new phy port. once the current cell transfer on the transmit utopia 2 interface is complete and the new phy port has responded, the new cell will be transferred on the transmit utopia 2 interface. with an 8-bit utopia bus there is a maximum one clock cycle delay between back to back cells w hen switching is be ing done wit hout a tag, and there is a maximum five clock cycle delay if a four byte tag is being used. there is a maximum three clock cycle delay betw een back to back cells in 16-bit utopia mode without a tag, and a maximum five clock cycle delay if a four byte tag is being used. there are several registers associated with the utopia 2 transmit interface. in-stream ? programming cells are used to program the regis- ters, which are described in the utopia 2 transmit register table. txref is a 8khz reference clock output generated from refclk. refclk is a 8khz reference clock input used to generate the txref clock signal. txled indicates if there is activity on the transmit utopia 2 bus. this signal asserts high when a cell is transferred over the bus, and will stay high for 2 22 tclk cycles. at 40mhz this is approximately 0.1 seconds. txprty is a parity bit for txdata[15:0] bus. the txaddr[4:0] bus is fully utopia level 2 compliant and follows the mphy cell-level handshake with one tclav as described in the utopia level 2 specification. when a cell is transferred on the transmit dpi interface the subport address is analyzed and ext racted by the 77v011. the subport address is then interleaved with the null phy subport address (0x1f) and output on the txaddr[4:0] bus to query the corresponding phy port. upon detecting a high tclav the 77v011 will assert tenb low, tsoc and the first valid byte/word of data. the current phy subport address will be
12 of 43 march 15, 2001 IDT77V011 figure 5 single cell transfer with no cell transfer in progress figure 6 back-to-back cell transfer on transmit utopia 2 bus $% $% ! & ! ' $% ( ' configuration 1 8001 0 drop tx cell 0 - 1 0 drop a cell with an invalid subport address. "0" do not drop the cell, "1" drop the cell. configuration 2 8002 [1:0] stall tx 0x2 0x0 selects whether or not to stall the pipeline if the phy trans- mit fifo is full. "0" drop cell, "1" stall pipeline indefinitely, "2" stall pipeline for stall cycles. [6:2] max subports 0x00 - 0x1e 0x1e indicates the maximum subport address value for the phy(s) connected to the transmit utopia 2 interface. configuration 3 8003 [7:0] stall tx cycles 0x00 - 0xff 0xff number of tclk cycles the interface has to stall the pipe- line when the phy transmit fifo is full. this field is valid only if the stall tx for stall cycles option is selected. status 8009 2 tx cell dropped 0 - 1 0 indicates if any cells have been d ropped at the transmit utopia 2 interface. this is a status indicator for the stall tx bit of the configuration 2 register. "0" no cells have been dropped, "1" a cell was dropped because the phy did not respond. table 3 utopia 2 receive register table 1 tclk (output) tclav (input) tenb (output) 5348drw07 tsoc (output) txdata[7:0] (output) 51 50 49 48 47 0 46 . 1f 1b 1f 1b 1f 1b txaddr[4:0] (output) 1b 1f 1b 1f 1b tclk (output) tclav (input) tenb (output) tsoc (output) txdata[7:0] (output) 2 1 53 . 1f 1b 1f 1b 1f 04 txaddr[4:0] (output) 1b 1f 1b 1f 1b 5348drw08 52 51 50 49 48 47
13 of 43 march 15, 2001 IDT77V011 " " " " " " " " the data path interface (dpi) is a synchronous bus interface designed to transfer atm cells between two devices. the 77v011 dpi interface will support either a 4-bit wide data bus (dpi-4) or an 8-bit wide data bus (dpi-8). there are separate transmit and receive interfaces, with all signals being sampled on the rising edge of their respective clock. " " " "

! ! ! ! " " " " the dpi receive interface is used to transfer cells from the 77v011 to the idt switchstar or other dpi device. it supports either a 4-bit or 8-bit output data bus (drxdata[7:0]) and follows the standard dpi timing characteristics as described in the dpi specification. other signals associated with this interface are dpi receive start of frame (drxfrm), and dpi receive clock (drxclk). drxclk operates at a frequency less than or equal to sysclk. depending on the dpi mode selected this clock will be either an input or an output. in normal mode drxclk is an input to the 77v011, and its frequency must be less than or equal to sysclk. in switch mode drxclk is a continuous clock generated by the 77v011, with its frequency being equal to sysclk. there is no flow control in switch mode, as it is assumed that the idt switc hstar will be able to a ccept all incoming cells (non-blocking). programming the clock direction is done at reset. the dpi mode is selected with the mgmt[3] signal at reset, with the condition of mgmt[3] being stored in the dpi mode bit of the mode select register. setting mgmt[3] ="0" selects switch mode (output), while setting mgmt[3] ="1" selects normal mode (input). the dpi bus size is selected with the mbus[10] pin at reset, with the condition of mbus[10] being stored in the dpi size bit of the mode select register. setting mbus[10] ="0" selects a 4-bit data bus, while setting mbus[10] ="1" selects an 8-bit data bus. drxfrm is the start of frame marker. this signal is one drxclk cycle long and is asserted high one drxclk cycle before the first nibble/byte of valid data. " " " "
"
"
"
" the dpi transmit interface is used to transfer cells from the idt switchstar or other dpi device to the 77v011. it supports either a 4- bit or 8-bit input data bus (dtxdata[7:0]) and follows the standard dpi timing characteristics as described in the dpi specification. other signals associated with this interface are dpi transmit start of frame (dtxfrm) and dpi transmit clock (dtxclk). dtxclk operates at a frequency equal to sysclk. dtxclk can be stopped to control data flow to the phy device. dtxfrm is the start of frame marker. this signal is one dtxclk cycle long and is asserted high one dtxclk cycle before the first valid nibble/byte of data. # # # # " " " " " " " " ! ! ! !

byte swapping must be performed to convert the 8 or 16-bit transmit and receive of the utopia interface to the 4 or 8-bit transmit and receive of the dpi interface. in 4-bit dpi mode cell formatting is big endian, or upper nibble first, while in 8-bit dpi mode cell formatting is done little endian to match the idt 77v400 switching memory. the utopia to dpi conversion table illustrates how the 77v011 performs cell formatting in 4 and 8-bit dpi mode. figure 7 nibble mode one cell transfer on receive dpi bus $% $% ! & ! ' $% ( ' mode select 8006 0 dpi size 0 - 1 defined by pin selects the size of dpi data bus. "0" 4-bit dpi transmit and receive data bus, "1" 8-bit dpi transmit and receive data bus. 1 dpi mode 0 - 1 defined by pin selects drxclk direction. "0" switch mode (output), "1" nor- mal mode (input). table 4 utopia 2 receive register table 0 1 2 3 105 104 103 drxclk (input/ output) drxfrm (output) drxdata[3:0] (output) 5348drw09
14 of 43 march 15, 2001 IDT77V011 figure 8 nibble mode back-to-back cell transfer on receive dpi bus figure 9 nibble mode one cell transfer on transmit dpi bus figure 10 nibble m ode back-to-back cell transfer on transmit dpi bus )*
+*
bit 7 bit 0 bit 3 bit 0 gfc vpi[7:4] gfc vpi[3:0] vpi[15:12] vpi[7:4] vpi[11:4] vpi[3:0] )*
)*
bit 7 bit 0 bit 7 bit 0 gfc vpi[7:4] gfc vpi[7:4] vpi[3:0] vpi[15:12] vpi[3:0] vpi[15:12] vpi[11:4] vpi[11:8] vpi[7:4] figure 11 utopia to dpi conversion 0 1 2 3 105 104 103 drxclk (input/ output) drxfrm (output) drxdata[3:0] (output) 5348drw10 105 104 0 01 23 105 104 103 dtxclk (output) dtxfrm (input) dtxdata[3:0] (input) 5348drw11 . 0 1 2 3 105 104 103 dtxclk (output) dtxfrm (input) dtxdata[3:0] (input) 5348drw12 105 104 0
15 of 43 march 15, 2001 IDT77V011

pull-up or pull-down resistors must be connected to mbus[11:0], mgmt[3:2] and txaddr[3:0] signals, on the pcb, to select desired register values. the sysrst signal must be asserted for at least one sysclk cycle to load the desired values. on the rising edge of sysrst the 77v011 will begin loading the register values, which takes an additional 16 sysclk cycles. during this 16 clock cycle period all outputs will be tri-stated.

the 77v011 has the option to change the read only pin configurable registers to read/write registers. writing a one to the override pin configuration bit of the pin controls register will change the pin config- urable registers from read only to read/write. this allows the 77v011 configuration parameters to be changed during normal operation. see pin configuration table for register description.

the system reset (sysrst ) pin or an in-stream ? cell carrying the reset command (message type id 0x3) will reset the 77v011 and the phy devices. the sysrst pin must be asserted low for a minimum of 100ns, while the in-stream ? (internal) reset command will keep the 77v011 in reset for 35 sysclk cycles. the 77v011 will remain in reset for 16 sysclk cycles after the deassertion of sysrst , or the internal reset in the case of a reset command. all outputs w ill be tri-stated starting two sysclk cycles after the assertion of sysrst or the internal reset, and will stay tri-stated for 24 sysclk cycles after the deassertion of sysrst or internal reset. the phyrst pin will then assert low resetting the phy devices for eight additional sysclk cycles. after the eight clock cycle period phyrst pin will deassert high. eight clock cycles may not be long enough to properly reset some phy devices. in this case a pull down resistor should be connected to the phyrst pin. this will allow the phyrst pin to be asserted as soon as it is tri-stated, which will lenten the time that the phyrst pin is a logical zero. the phy can be reset at any time by writing a one to the phy reset bit of the reset register. writing a one will force the external phyrst pin low for 16 sysclk cycles. this register bit will return to zero once the reset command is completed. this method will only reset the phy device connected to the phyrst pin. %
& the 77v011 can run at a maximum sysclk speed of 50mhz. the dpi clocks must run at 40mhz, or greater, to achieve 155.52mbps data rate with over head. the clock s peed vs. b andw idth table lists some of the possible data rates and the clock frequencies required to achieve them. , - $ $% mbus[2:0] tx tag size number of bytes to remove from the cell. valid values are from zero to four bytes. tx tag [2:0] mbus[3] tx tag location location of the transmit tag. "0" transmit tag located at the beginning of the cell, "1" trans- mit tag located at the end of the cell. tx tag [4] mbus[4] tx add hec add a hec placeholder to the cell. "0" do not add hec placeholder, "1" add hec plac eholder. tx tag [3] mbus[7:5] rx tag size number of bytes to add to the cell. valid values are from zero to four bytes. rx tag [2:0] mbus[8] rx tag location location of the receive tag. "0" receive tag located at the beginning of the cell, "1" receive tag located at the end of the cell. rx tag [4] mbus[9] rx hec remove hec byte from cell. "0" do not remove hec byte, "1" remove hec b yte. rx tag [3] mbus[10] dpi size dpi bus size. "0" 4-bit transmit and receive data bus, "1" 8-bit transmit and receive data bus. mode select [0] mbus[11] utopia 2 size utopia 2 bus size. "0" 8-bit transmit and receive data bus, "1" 16-bit transmit and receive data bus. mode select [2] mgmt[2] mmode management mode. "0" utility bus style, "1" ut opia 2 style. m ode select [3] mgmt[3] dpi mode drxclk direction. "0" switch mode (output), "1" normal mode (input). mode select [1] txaddr[2:0] subport byte location transmit and receive subport address location. indicates what byte of the header the transmit and receive subport addresses are located in. valid values are zero to three. tx subport position [2:0] and rx subport position [2:0] txaddr[3] init from eeprom five byte write from eeprom to in-stream ? cell header and in-stream ? subport registers at reset. "0" do not write f ive byte val ue, "1" write five byte value. mode select [4] table 5 reset configuration pins
16 of 43 march 15, 2001 IDT77V011 figure 12 utility bus read operation $% $% ! & ! $% ' ( ' pin controls 801a 0 override pin configuration 0 - 1 0 enables writing to pin configurable registers during normal operation. "0" pin configurable registers are read only, "1" pin configurable registers are read/write registers table 6 pin configuration table .
$ //'011 23 . software reset (in-stream tm )x x sysrst (external pin) x x phyrst (register bit) x table 7 reset table 345 6278 ! "# 45 9 $45 6278 ! "# 45 9 $45 6278 calculated bandwidth of utopia interface (cell rate in mbps) :;
6 < = 8 :>
6(
( = ? 2@8 32 4 32 8 16 125.6 113.8 40 4 40 8 20 157 142.2 50 4 50 8 25 196.3 177.8 16 8 16 8 16 125.6 113.8 25 8 25 8 25 196.3 177.8 33 8 33 8 33 259.1 234.7 32 8 32 16 16 242.3 235 50 8 50 16 25 378.6 367.2 table 8 clock speed verses bandwidth table address ale phycs add/data[7:0] rd read data from phy 5348drw13 t alpw t aal t ala t alr t rdpw t drs t drh sysclk t pale t pphy (i) (o) (i/o) (o) (o)
17 of 43 march 15, 2001 IDT77V011 " " " " the management interface is a multi-function interface used to read and write to the phy registers during normal operation, and to configure the pin configurable registers during reset. signals associated with the management interface are bus mode (bmode), management bus (mbus[11:0]), management data bus (mdata[7:0]), management 1 (mgmt[1]), management 2 (mgmt[2]), management 3 (mgmt[3]), management 4 (mgmt[4]), management 5 (mgmt[5]), phy reset (phyrst ) and phy interrupt (phyint ). during normal operation the management interface is used to access the phy registers. the 77v011 will operate in either a utility bus mode or the management mode described in the utopia 2 mode section a2.4.2 of the utopia level 2 spe cification. refer to the address map for addressing description of the phy registers. #

' the utility bus is used to access and configure the phy registers. read and write commands are sent to the phy with in-stream ? programming cells. mbus[11:0] are active low chip select enable (cs [12:1]) signals used to select a particular phy device. these are active low signals used to validate read, write, or addressing operations on the utility bus. mdata[7:0] is a multiplexed byte wide address and data bus (ad[7:0]) used to address, read and write data on the utility bus. mgmt[1] is an active low chip select enable (cs [0]) signal used to validate read, write, or addressing operations on the utility bus. mgmt[2] is an active low read enable (rd ) used as an enable to read data f rom an addressed location on mdata[7:0]. mgmt[3] is an active low write enable (wr ) used as an enable to write data to an addressed location on mdata[7:0]. mgmt[5] is an active high address latch enable (ale) used to latch the address in the address phase of a utility bus read or write command. phyrst is an active low phy reset signal. phyrst can be asserted by writing to the phy reset bit in the phy reset register. phyint is an active low interrupt signal. this signal is driven by the phy layer and indicates that an interrupt has occurred. the interrupt must be cleared by the controlling cpu before another interrupt event can be reported. registers associated with the management interface are described in the management register table. #

#

#

#

' ' ' '

a utility bus read is initiated by an in-stream ? programming cell. once the 77v011 interprets the cell as a read command it will drive phycs , ale, rd , and ad[7:0]. the phy samples the address on the falling edge of ale. once phycs and rd assert the bus tristates and switches to an input for the phy to place data on. the phy drives the bus until the rising edge of phycs or rd . one utility bus read can include up to 32 bytes of data. #

#

#

#

' ' ' ' (
(
(
(

a utility bus write is initiated by an in-stream ? programming cell. once the 77v011 interprets the cell as a write command it will drive phycs , ale, wr , and ad[7:0]. the phy samples the address on the falling edge of ale. once phycs and wr assert the 77v011 will write data to the phy. one utility bus write can include up to 32 bytes of data. figure 13 utility bus write o peration $% $% ! & ! $% ' ( ' mode select 8006 3 utopia manage- ment mode 0 - 1 defined by pin selects type of management interface to use. "0" utility bus style, "1" utopia 2 management style. phy reset 8007 0 phy reset 0 - 1 0 phy reset. "0" do not reset the phy device, "1" reset the phy device (phyrst signal will be asserted low for at least 16 sysclk cycles). table 9 pin configuration table address ale phycs add/data[7:0] wr writedatatophy 5348drw1 t alpw t aal t ala sysclk t pale t pphy t alw t dwh t dws (i) (o) (o) (o) (o) t wrpw t aw
18 of 43 march 15, 2001 IDT77V011 #" $ #" $ #" $ #" $ the utopia 2 management interface is used to access and configure the phy registers. read and write commands are sent to the phy with in-stream ? programming cells. bmode selects the type of utopia 2 management mode interface to be used as defined by the utopia level 2 specification. setting bmode ="0" selects the motorola style, while setting bmode ="1" selects the intel mode. mbus[11:0] are address bits in this mode and are used to access the internal registers of a particular phy device. the addressing scheme of what phy and register address is user definable. an example would be to use the upper five bits (mbus[11:7]) for the subport number and the lower seven bits (mbus[6:0]) for the phy register address. mdata[7:0] is a byte wide bi-directional data bus used to read data from or write data to a phy device. mgmt[2] is an active low signal used as an enable to r ead data from the addressed location on the data bus when bmode = "1", and when bmode = "0" it is an active low enable used to read data from the phy layer, or strobe write data to the phy. mgmt[3] is an active low write enable used to write data to an addressed location when bmode = "1", and when bmode = "0" it defines the current transaction as a read, if equal to one, or a write, if equal to zero. mgmt[4] is an active low signal that indicates when a transfer on the mdata[7:0] bus is complete. phyrst is an active low phy reset signal. phyrst can also be asserted by writing to the phy reset bit in the phy reset register. phyint is an active low interrupt signal. this signal is driven by the phy layer and indicates that an interrupt has occurred. the interrupt must be cleared by the controlling cpu before another interrupt event can be reported. registers associated with the management interface are described in the management register table. # # # # " $ " $ " $ " $

a read is initiated by the 77v011 driving the address bus (mbus[0:11]), asserting sel (mgmt1) = "0" and asserting the appro- priate strobe, which is dependant on the condition of bmode. the phy then drives rdy / dtack (mgmt[4]) and the data bus (mdata[0:7]). the phy will de-assert rdy / dtack to signal the completion of the data cycle. when bmode = "1" the data is strobed by asserting rd / ds , (mgmt[2]) = "0", with the wr / rw , (mgmt[3]) = "1". when bmode = "0" the data is str obed by setting the wr / rw and rd / ds = "1". # # # # " $ " $ " $ " $ (
(
(
(

a write is initiated by the 77v011 driving address bus (mbus[0:11]), the data (mdata[0:7]), and asserting the appropriate strobe. the phy will drive rdy / dtack (mgmt[4]) to specify the beginning and end of the cycle. when bmode = "1" the data is strobed setting wr / rw (mgmt[3]) and rd / ds (mgmt[2]) = "1". when bmode = "0" the data is strobed by setting rd / ds = "1" and setting wr / rw = "0". figure 14 utopia 2 parallel interface read cycle data[7:0] sel addr[11:0] rd/ds 5348drw 1 t adrs t rdpw (i/o) (o) (o) (o) wr/rw (o) rdy/dtack (i) rd/ds (o) wr/rw (o) rdy/dtack (i) t sers t darv t dariv t adrh t selrh t rdyrt t rdyrv b m o d e = " 0 " b m o d e = " 1 "
19 of 43 march 15, 2001 IDT77V011 figure 15 utopia 2 parallel interface write cycle . $ ! ( 68 ( bmode ?? bmode mbus[0] tx tag size[0] cs [1] addr[0] mbus[1] tx tag size[1] cs [2] addr[1] mbus[2] tx tag size[2] cs [3] addr[2] mbus[3] txloc cs [4] addr[3] mbus[4] txhec cs [5] addr[4] mbus[5] rx tag size[0] cs [6] addr[5] mbus[6] rx tag size [1] cs [7] addr[6] mbus[7] rx tag size [2] cs [8] addr[7] mbus[8] rxloc cs [9] addr[8] mbus[9] rxhec cs [10] addr[9] mbus[10] dpi_sel cs [11] addr[10] mbus[11] utopia_sel cs [12] addr[11] mdata[7:0] ? add/data[7:0] data[7:0] mgmt[1] ? cs [0] sel mgmt[2] mmode rd rd /ds mgmt[3] dpi_mode wr wr /rw mgmt[4] ?? rdy /dtack table 10 multiplexed management interface (part 1 of 2) data[7:0] sel addr[11:0] rd/ds 5348drw 1 t adws t wrpw (i/o) (o) (o) (o) wr/rw (o) rdy/dtack (i) rd/ds (o) wr/rw (o) rdy/dtack (i) t sews t daws t dawh t selwh t rdywt t rdywv b m o d e = " 0 " b m o d e = " 1 "
20 of 43 march 15, 2001 IDT77V011 mgmt[5] ? ale ? phyrst ? phyrst phyrst phyint ? phyint phyint , mgmt[1] cs [0] o chip select[0]. active low phy chip select. mbus[11:0] cs [12:1] o chip select[12:1]. active low phy chip select for 12 additional phys con- nected to this device. mgmt[2] rd o read enable. active low read enable. mgmt[3] wr o write enable. active low write enable. mgmt[5] ale o address latch enable. active high address latch enable. mdata[7:0] addr/data[7:0] i/o address/data bus. bidirectional address and data bus. phyint phyint i phy interrupt. active low phy interrupt. phyrst phyrst o phy reset. active low phy layer reset. table 11 utility bus management interface , bmode bmode i bus mode. "0" selects motorola management mode interface, "1" selects intel management mode interface. mbus[11:0] addr[11:0] o address bus used to select a register in a particular phy device. mdata[7:0] data[7:0] i/o byte wide bidirectional data bus. mgmt[1] sel o select. active low signal used to validate addr[11:0] for a r ead or write opera- tion. mgmt[2] rd /ds o read or data strobe. if bmode = "0" then r ead data from the phy layer, or strobe write data to the phy layer. if bmode ="1" then read data from the addressed location onto the data [7:0] bus. mgmt[3] wr /rw o write or read/write. if bmdoe ="0" t hen access is a read if high and a write if low. if bmode ="1" then write data from data[7:0] to the addressed location. mgmt[4] rdy /dtac k i ready or data acknowledge. tri-stateable signal used to acknowledge the end of a transfer over data[7:0] bus. phyrst phyrst o phy reset. active low phy layer reset. phyint phyint i phy interrupt. phy layer interrupt, with open-drain active low ou tput. table 12 utopia 2 management interface . $ ! ( 68 ( table 10 multiplexed management interface (part 2 of 2)
21 of 43 march 15, 2001 IDT77V011 " " " " the eeprom interface is an optional device that can be used for initialization and discovery/identify commands. the data is broken up into five fields. bytes [4:0] contain a 5-byte value that can be read at reset and placed in the in-stream ? cell header and in-stream ? subport regis- ters. bytes [3:0] are used for the in-stream ? cell header registers, while byte [4] is used for the in-stream ? subport register. bytes [7:5] are not used at this time, while bytes [39:8] contain 32-bytes of data, which is read when a discovery/identify comm and is encountered. bytes [40:127] are reserved and bytes [128:255] are user defined. the regis- ters associated with the eeprom are listed in the eeprom register table. signals associated with this interface are clock (eeclk), chip select (eecs ), data out (eedout), and data in (eedin). eeclk is generated from sysclk and is an output of the 77v011. eecs is an active low chip select signal used to validate a read or write operati on. eedout is a serial data output pin to the eeprom. eein is a serial input data pin from the eeprom. at reset txaddr[3] selects whether or not to write the first f ive bytes stored in the eeprom to the in-stream ? cell header and in-stream ? subport registers. setting txaddr[3] to a zero will select not to write the five byte value, while setting it to a one will write the value to the registers. the state of the txaddr[3] signal, at reset, is stored in the init from eeprom bit of the mode select register. the eeprom can be controlled with the eeprom registers, which include mux select (eeprom mux sel), clock out (eeprom clock out), chip select (eeprom chip select), data out (eeprom out), and data in (eeprom in). eeprom mux select indicates whether the eeprom pins will be connected to the internal logic, or to the eeprom registers. when connected to the internal logic 32-bytes of data are read from the eeprom when a discovery/identify comm and is filte red. controlling the eeprom from the registers enables the user the flexibility of reading and writing the eeprom at any time. programming is accomplished with in-stream ? cells regardless of the method used to access the eeprom. eeprom clock out is used to clock the eeprom when it is being controlled by the registers. this register must be written to twice to execute one eeprom clock cycle. you must write to the clock register to perform a read or write comm and. eeprom chip select validates transactions on the eeprom inter- face when being controlled by the eeprom registers. eeprom out is a 1-bit register used to output data to the eeprom. eeprom in is a 1-bit register used to input data from the eeprom.

a subport address is used to select a phy port. the address can be up to five bits wide and be located anywhere in the first four bytes of the atm cell, or first eight bytes of the cell if a four byte pre- pended tag is being used. it can start in any bit location of a byte and can span over the byte boundary. the 77v011 uses the transmit subport field in determining how to route the cell. normal cells have a phy subport value from zero to the value stored in max subports bits of the configuration 2 register. the max subport can be any value between zero and 30, as the utopia 2 specification allows a total of 31 phy ports to be connected to a utopia 2 interface. the cell will be dropped if a subport greater than the max subports value is used. once the subport field is read the 77v011 can replace the subport value with the value contained in the new subport bits of the modify tx subport register. overwriting is determined by the replace subport bit of the modify tx subport register. only the data cells are affected when the 77v011 is configured to overwrite the subport field. the subport field of in-stream ? cells are not altered. the tx byte location bits of the tx subport position register indicate what byte of the header the subport field starts in. valid values are zero to three without using a tag, and zero to seven when using a tag. the subport field can start in any byte location of the header. this value is programmed at reset with txaddr[2:0] pins. the 77v011 will concate- nate the transmit subport field if any part of the s ubport f ield extends into the payload area of the cell. this is to ensure that the payload will not be altered. bits [5:3] of the tx subport position register contain the tx bit loca- tion. this value indicates what bit in the byte the s ubport msb is located in. a value of zero means that bit zero of the selected byte is msb, bit 7 of the next byte is msb-1, etc.... the subport can start on any bit of a byte and span multiple bytes. the number of bits to be used for the transmit subport field is programmed in the tx subport width field bits of the subport configura- tion 1 register. the subport width can be any value between one and five, with the default value being five. a special mode of operation occurs when the tx subport width is set to zero. when this is done, the cell will be passed to the transmit utopia bus unchanged, and the polled address will be 0x0. this mode of operation is intended for system configurations with a single phy device. registers associated with the transmit cell routing are defined in the transmit cell routing register table.
22 of 43 march 15, 2001 IDT77V011 figure 16 eeprom memory map figure 17 register address map 0 4 5 7 8 39 40 127 128 255 user defined reserved discovery/identify cell data reserved in-stream? cell header 5348drw17 byte in-stream? subport 3 phy #2 registers 77v011 registers reserved 0x000000 0x0000ff 0x000100 0x000f00 0x008000 0x008024 0x008025 0xffffff 5348drw18 aligned on byte boundary (8-bits = 1 byte) phy #1 registers phy #0 registers phy #30 registers 0x0001ff 0x000200 0x0002ff 0x000300 0x000e00 0x000eff reserved 0x007fff phy #29 registers 0x000d00 0x000dff 0x000cff phy #28 registers 0x000c00 0x000bff
23 of 43 march 15, 2001 IDT77V011

! ! ! !

the receive cell routing is done by inserting the originating phy port address into the receive subport address field. the 77v011 uses the subport field in determining how to route the cell. normal cells have a phy subport value from zero to the value stored in max subports bits of the configuration 2 register. the max subport can be any value between zero and 30, as the utopia 2 specification allows a total of 31 phy ports to be connected to a utopia 2 interface. in-stream ? cells have a subport value that is defined in the in- stream ? subport bits of the subport configuration 1 register. in order for in-stream ? cells to be filtered properly two things must happen. first, the subport value within the received cell must match the in- stream ? subport, tx subport width, tx byte location, and the tx bit location register fields. second, the received cell's header, excluding the pt, clp and hec fields, must match the in-stream ? cell header register bits [31:4]. this dual check allows the in-stream ? subport value to be the same as a valid phy s ubport address. the rx byte location bits of the rx s ubport position register i ndicate what byte of the header the subport field starts in. valid values are zero to three without using a tag, and zero to seven when using a tag. the subport field can start in any byte location of the header. this value is programmed at reset with txaddr[2:0] pins. the 77v011 will concate- nate the receive subport field if any part of the s ubport f ield extends into the payload area of the cell. this is to ensure that the payload will not be altered. bits [5:3] of the rx subport po sition register contain the rx bit loca- tion. this value indicates what bit in the byte the s ubport msb is located in. a value of zero means that bit zero of the selected byte is msb, bit 7 of the next byte is msb-1, etc.... the subport can start on any bit of a byte and span multiple bytes. the number of bits to be used for the receive subport field is programmed in the rx subport width field bits of the s ubport c onfigura- tion 2 register. the subport width can be any value between one and five, with the default value being five. the rx out of range address mask registers validate the vpi/vci field, default value is 0x000000. this 24-bit value is used to compare against the incoming cell headers on the receive utopia 2 interface. a bit wise and operation is done between each bit of the incoming cell header and its corresponding bit of the rx out of range address mask register. the address range error bit of the status register will be set to a one if the result of any of these and operations is a one, indicating an invalid cell has been received. a notification cell will be generated if the rx address error bit of the notification mask register is set to a one. another notification cell will be generated 25ms after the error occurred if the address range error bit has not been cleared. additional notifica- tion cells will be generated on 12ms intervals, thereafter, until the address range error bit is cleared. the rx out of range subport bits of the rx out of range s ubport register stores the subport address of the violating rx out of range cell. the cpu can read this register to determine what phy port the invalid cell came from. the rx out of range subport bits will be overwritten when a new address range error occurs. clearing the interrupt is done by writing a one to the address range error bit of the status register. writing a one will clear the interrupt and reset the register bit to a zero. registers associated with the receive cell routing are defined in the receive cell routing register table. $% $% ! & ! $% ' ( ' mode select 8006 4 init from eeprom 0 - 1 defined by pin five byte write from eeprom to in-stream ? cell header and in- stream ? subport registers at reset. "0" do not write five byte value, "1" write five byte value to registers. pin controls 801a 3 eeprom mux select 0 - 1 0 indicates if the eeprom interface will be connected to the internal logic or the eeprom registers. "0" connected to internal logic, "1" connected to eeprom registers. 4 eeprom clock out 0 - 1 0 eeprom clock when eeprom interface is c onnec ted to the eeprom registers. "0" clock low, "1" clock high. 5 eeprom chip select 0 - 1 0 eeprom chip select when eeprom interface is connec ted to the eeprom registers. "0" eeprom interface is selected, "1" eeprom inter- face is not selected. 6 eeprom out 0 - 1 0 eeprom serial output when eeprom interface is connected to the eeprom registers. 7 eeprom in 0 - 1 0 eeprom serial input when eeprom interface is connected to the eeprom registers. table 13 pin configuration table
24 of 43 march 15, 2001 IDT77V011 figure 18 transmit s ubport int erpreter figure 19 example subport programming in-stream? subport bits[4:0] of subport configuration register replace subport bit5 of modify tx subport register new subport bits[4:0] modify tx subport register cell interpreter process in-stream? cell mux dpi tx utopia tx 5348drw19 01 2 3 4 5-52 76 5 43 2 10 xxxxx bit normal cell byte 0 52 76 5 43 2 10 11111 bit dpi tx (incoming) utopia tx (outgoing) 5348drw20 register content max subports 0x1e in-stream? subport 0x07 (matches bits[5:1] of in-stream? cell header byte 2 subport width 0x5 in-stream? cell header byte 3 0x00 replace subport 1 in-stream? cell header byte 2 0xe0 bit location 0x5 in-stream? cell header byte 1 0x01 byte location 0x2 in-stream? cell header byte 0 0xf0 new subport 0x1f x = any valid subport address 01 2 3 4 5-52 76543210 0011 1 bit byte 0 52 in-stream cell dpi tx (incoming) filtered by cell interpreter
25 of 43 march 15, 2001 IDT77V011 " " " " a tag can be added to the cell in either the transmit or receive d irec- tion. it can be up to four bytes long, and be added to the beginning or end of the cell. programming a tag for both the transmit and receive direction is done with external pins and internal registers, with each direction being individually programmed. registers associated with the tag are listed in the transmit and receive tag register table.

! ! ! ! a tag is added in the receive direction by first configuring the external pins and then programming the internal registers. the external pins are multiplexed with the mbus[9:5] pins. the rx tag size [2:0] indicates the size of the tag to be appended. this value can be from zero to four and is set with the mbus[7:5] pins at reset. this value is stored in rx tag size bits of the rx tag regis ter. the rx tag location indicates whether the tag is located at the beginning or end of the cell. setting this bit to a zero indicates that the tag is appended to the beginning of the cell, while setting this bit to a one indicates the tag is appended to the end of the cell. this register bit is programmed at reset with the mbus[8] pin and is stored in rx tag location bit of the rx tag register. rx remove hec is defined by pin mbus[9] at reset and indicates whether the hec byte should be removed or not. setting this bit to zero will indicate not to remove the hec byte, while setting it to a one will remove the hec byte. this value is stored in the rx remove hec bit of the rx tag register. the tag 1, 2, 3 and 4 registers contain the header value used for the tag. this value is only used for all cells. the default value is 0x000001fx, which can be changed by writing to the registers with in- stream ? cells. rx move pt/clp bit, of the configuration 1 register, is an option to move the pt and clp fields of the atm cell header into the four bytes of tag area. setting this bit to zero will not move these fields, while setting it to a one will move these fields from the incoming cell header to the tag area. this enables a dpi device or switchstar that is switching on the tag area to find oam cells, do low priority cell discards and efci processing. this option is only valid if using all four bytes of tag and switching is being done on the tag appended to the beginning of the cell. this option is not valid when a tag is appended to the end of the cell. registers associated with the receive tag are listed in the receive tag register table.

a transmit tag is programmed by first configuring the external pins and then programming the internal registers. the external pins are multi- plexed with the mbus[4:0] bus. the copy efci bit, of the configuration 1 register, selects whether or not to or the efci bit of the cell header with the efci bit of the tag area appended to the beginning of the cell, and place the or'ed efci bit in the cell header. setting this bit to zero will select not to or the efci bits, while setting it to a one will or the efci bits. this option is not valid when the tag is appended to the end of the cell. tx tag size [2:0] indicates the size of the tag to be removed from the cell. this value is set with the mbus[2:0] pins at reset and is stored in bits [2:0] of the tx tag register. valid values for this field are zero to four. tx tag location indicates whether the tag is located at the begin- ning or end of the cell. setting this bit to a zero indicates the tag is located at the beginning of the cell, while setting this bit to a one indi- cates that the tag is located at the end of the cell. this value is programmed at reset with the mbus[3] pin and is stored in the tx tag location bit of the tx tag register. tx add hec indicates if a hec placeholder should be added to the cell. setting this bit to a zero indicates not to add the hec byte, while setting it to a one indicates to add the hec byte. this value is programmed at reset with the mbus[4] pin and is stored in tx add hec bit of the tx tag register. the tag 1, 2, 3 and 4 registers contain the header value used for the tag. this value is only used for in-stream ? cells. the default value is 0x000001fx, which can be changed by writing to the registers with in- stream ? cells. the tx move pt/clp bit, of the configuration 1 register, is an option to move the pt/clp fields from the 4-byte tag area appended to the beginning of the cell to the cell header. setting this bit to a zero will not move the fields, while setting it to a one will move the pt/clp fields. this option is not valid when the tag is appended to the end of the cell. registers associated with the transmit tag are listed in the transmit tag register table.
26 of 43 march 15, 2001 IDT77V011 $% $% ! & ! $% ' ( ' configuration 2 8002 [6:2] max subports 0x00 - 0x1e 0x1e indicates the maximum subport address for the phy's connected to the transmit utopia 2 interface. subport configuration 1 8013 [4:0] in-stream ? subport 0x00 - 0x1f 0x00 subport address used to filter in-stream ? programming cells. [7:5] tx subport width 0x0 - 0x7 0x5 programs how many bits will be used for subport addressing in the trans- mit direction. modify tx subport 8014 [4:0] new subport 0x00 - 0x1f 0x00 new value used to replace s ubport address in outgoing cells. this value will only be used if the replace subport bit of the modify tx subport regis- ter is set to a one. 5 replace subport 0x0 - 0x7 0 indicates whether or not to replace the subport address in outgoing cells. "0" do not replace the subport address, "1" replace the subport address with the value in the new subport bits of the modify tx subport register. tx subport position 8015 [2:0] tx byte location 0x0 - 0x7 defined by pin indicates what byte of the transmit cell header the subport address starts in. the subport address can cross the byte bo undary. [5:3] tx bit location 0x0 - 0x7 0x5 indicates what bit of the byte defined by the tx byte location bits of the tx subport position register the msb of the transmit s ubport addr ess sta rts. the subport address can cross the byte bo undary. table 14 transmit cell routing register table $% $% ! & ! $% ' ( ' notification mask 8008 1 rx address error 1 - 0 0 mask address range error notification. "0" no event notification cell will be generated when a rx out of range address error occurs, "1" generate event notification cell when a rx out of range address error occurs. status 8009 1 address range error 1 - 0 0 address range error indication when an address range error occurs. "0" no address range error detected, "1" address range error has been detected. timeout status 800a 1 address error status 1 - 0 0 indicates that a address error occurred more than 25ms ago, and address range error status bit has not been cleared. this bit will return to zero once the interrupt is cleared. "0" no address range errors detected, "1" address range error occurred more than 25ms ago and has not been cleared. rx out of range subport 800b [4:0] rx out of range subport 0x00 - 0x1f 0x00 the subport address of a cell containing an invalid cell header. rx out of range address mask byte 2 801c [7:0] address mask register [23:16] 0xff 0x00 value used to validate cells on the receive ut opia interface. rx out of range address mask byte 1 800d [7:0] address mask register [15:8] 0xff 0x00 value used to validate cells on the receive ut opia interface. rx out of range address mask byte 0 800e [7:0] address mask register [7:0] 0xff 0x00 value used to validate cells on the receive ut opia interface. subport configuration 2 8023 [2:0] rx subport width 0x0 - 0x7 0x5 programs how many bits will be used for subport addressing in the receive direction. rx subport position 8024 [2:0] rx byte location 0x0 - 0x7 defined by pin indicates what byte of the receive cell header the s ubport starts in. the subport address can cross the byte boundary. [5:3] rx bit location 0x0 - 0x7 0x5 indicates what bit of the byte defined by the rx byte location bits of the rx subport position register the msb of the receive subport address sta rts. the subport address can cross the byte bo undary. table 15 receive cell routing register table
27 of 43 march 15, 2001 IDT77V011 $% $% ! & ! $% ' ( ' configuration 1 8001 2 rx move pt/clp 0 - 1 0 selects whether or not to move the pt/clp fields from the cell header into the 4-byte tag area appended to the beginning of the cell. this option is not valid when the tag is appended to the end of the cell. "0" do not move the pt/clp to the 4-byte tag area, "1" move the pt/clp to the 4-byte tag area. rx tag 8005 [2:0] rx tag size [2:0] 0 - 4 defined by pin number of bytes to add to atm cell in the receive direction. valid val- ues are from zero to four. 3rx remove hec 0 - 1 defined by pin remove hec byte from cell. "0" do not remove the hec b yte from the cell, "1" remove the hec byte from the cell. 4rx tag location 0 - 1 defined by pin tag location in receive direction. "0" receive tag is located at the beginning of the cell, "1" receive tag is located at the end of the cell. tag byte 3 8016 [7:0] tag [31:24] 0x00 - 0xff 0x00 tag added to cell. tag byte 2 8017 [7:0] tag [23:16] 0x00 - 0xff 0x00 tag added to cell. tag byte 1 8018 [7:0] tag [17:8] 0x00 - 0xff 0x00 tag added to cell. tag byte 0 8019 [7:0] tag [7:0] 0x00 - 0xff 0x00 tag added to cell. table 16 receive tag register table $% $% ! & ! $% ' ( ' configuration 1 8001 1 copy efci 0 - 1 0 selects whether or not to or the efci bit of the cell header with the efci bit of the 4-byte tag area appended to the beginning of the cell, and place the or'ed efci bit in the cell header. this option is not valid when the tag is appended to the end of the cell. "0" do not or the efci bit to the 4-byte tag area, "1" or the efci bit to the 4-byte tag area. 3tx move pt/clp 0 - 1 0 selects whether or not to move the pt/clp fields from the 4-byte tag area appended to the beginning of the cell into the cell header. this option is not valid when the tag is appended to the end of the cell. "0" do not move the pt/clp fields to the cell header, "1" move the pt/ clp fields to the cell header. tx tag 8004 [2:0] tx tag size 0x0 - 0x4 defined by pin number of bytes to remove from the atm cell in the transmit direction. valid values are from zero to four. 3 tx add hec 0 - 1 defined by pin add a hec placeholder in the transmit direction. "0" do not add a hec placeholder, "1" add a hec placeholder. 4tx tag location 0 - 1 defined by pin tag location in transmit direction. "0" transmit tag is located at the beginning of the cell, "1" transmit tag is located at the end of the cell. table 17 transmit tag register table
28 of 43 march 15, 2001 IDT77V011 " )& " )& " )& " )& * * * *

in-stream ? programming cells are used to carry commands to the 77v011 and for the cpu to receive information from the 77v011. cells are received on the dtxdata[7:0] bus. all cells received on the dtxdata[7:0] data bus are filtered by the cell interpreter to determine if they are in-stream ? programming cells. in order to be recolonized in- stream ? programming cells have a unique cell header. the default value is 0x000001fx, which can be changed by writing to the in- stream ? cell header 1, 2, 3 and 4 registers, and have a s ubport value that matches the in-stream ? subport field of the s ubport conf iguration register. all four in-stream ? cell header registers can be written to in one four byte write with an in-stream ? cell. the bytes are written msb to lsb. the new cell header will be used for returning a reply notifica- tion cell, following the write ope ration. the 77v011 supports the following set of in-stream ? functions, discover/identify, reset, register read, register write, event notifica- tion and reply n otification. the discover/identify command is sent by the cpu to the 77v011, and is used to either discover the 77v011 or to ensure that the 77v011 is still attached (heart beat). the reset command is sent from the cpu to the 77v011, which indi- cates that the 77v011 must perform a hard reset and re-initialize itself to its default state. the register read command is used to read the value of one or more registers. up to 31-bytes can be read with one in-stream ? cell. the register write command is used to write a value to one or more registers. up to 31-bytes can be written with one in-stream ? cell. the event notification command is sent from the 77v011 to the cpu and indicates that an event has happened that requires cpu interven- tion. the reply notification command is sent from the 77v011 to the cpu in response to command cells sent by the cpu. the 77v011 will generate a reply notification response to a discover/identify, register read and register write command, but not for a reset command. this option is enabled by setting the acknowledge request bit in the message type field of the in-stream ? command cell. the in-stream ? cell format is broken up into six sections, which vary slightly depending on the type of command the cell caries. the first five bytes contain the cell header. the in-stream ? programming cell address is in the first 28-bits with the default value of gfc =0x0, vpi =0x0, vci =0x001f, pt/clp =0xx, where x=don't care. the remaining byte is the hec. bytes six and seven of the cell contain the transaction id informa- tion. this field is two bytes wide and is used to correlate messages requiring a reply to a command. this allows more than one command to be sent to a device without waiting for a reply notification cell, as the field is copied from the command cell to the reply notification cell. the 2-byte field is set to zero when an event notification cell is gener ated by the 77v011, with the zero value being valid for this condition only. it is up to the cpu to generate and manage values for it's in-stream ? commands and not re-use the value for some set am ount of time. byte 8 contains the mess age type f ield, which indicates what type of command the cell contains. bit location eight is not used. bit seven is the acknowledge request bit, which indicates if an acknowledgement to the command cell is r equi red or not. when a reply notification cell has to be returned this bit is set to a one. when the reply notification cell is returned the bit is reset to zero by the 77v011. this option is not valid with the reset command, which does not return a reply notification cell. bit six is the acknowledge bit which indicates whether the cell is a reply notification cell or a command cell. this bit is set to a zero when the cell is a command cell, and is set to a one, by the 77v011, when the cell is a reply notification cell. bits one thorough five are the message type indicator. there are currently five commands for this field. the discover/identify (value = 0x2) command, which will generate a reply notification cell with 32 bytes of device specific data located in the message data field. the reset (value = 0x3) command performs a reset on the 77v011. there is no reply notification cell returned for this command. the read registers (value = 0x5) command performs a read operation to a set of consecutive registers. the returned register data is contained in the message data field. the write registers (value = 0x6) command performs a write operation to a set of consecutive registers. the data to be written is contained in the message data field. the event notification (value = 0x8) command generates a event notification cell indicating that an interrupt has been detected. bytes 9 thorough 15 are the device id field. there are two formats to this field depending on the type of command the cell carries. when the cell contains either the register read/write, or event notification command this field must contain a value of 0x01 in byte location 9 to be valid. the remaining six bytes are not used and should contain zeros. when the cell contains the discovery/identify command this field contains data from the eeprom, with data from eeprom byte location 8 being written to the first byte position of this field. bytes 16 thorough 51 are the message data field. the layout of this field is dependant on the message type field. a read or write command will have a message data field divided into three sub fields. the first sub field is one byte wide and indicates how many bytes of data are valid in the data portion of the message data field. the second sub field is three bytes wide and contains the base address for the read or write command. the third sub field is the valid data and padding. valid data is written starting at the base address in accordance with the number of valid bytes indicator (first sub field). the remaining space, if any, is padded with zeros. a discover/identify command has a message data field divided into two sub fields.the first sub field is the first 25- bytes of the message data field, which contains up to 25 bytes read from the eeprom, starting at eeprom byte location 15. the remaining bytes are reserved. an event no tification comm and will have a message data field split into two sub fields. the first sub field is two bytes wide and contains an event number, which is always 0x 0100. the second sub field contains one byte of data (byte 18) indicating what type of event happened, which is described in the event notification table. the remaining bytes 19 to 51 are padding and contain zeros. bytes 52 and 53 contain the crc-10 trailer, with the upper six bits of byte 52 containing zeros. the crc-10 is generated and used in the same manner as in aal3/4 cells.
29 of 43 march 15, 2001 IDT77V011 $% $% ! & ! $% ' ( ' in-stream ? cell header byte 0 800f [7:0] in-stream ? header [31:24] 0x00 - 0xff 0x00 cell header used for in-stream ? programming cells. in-stream ? cell header byte 1 8010 [7:0] in-stream ? header [23:16] 0x00 - 0xff 0x00 cell header used for in-stream ? programming cells. in-stream ? cell header byte 2 8011 [7:0] in-stream ? header [15:8] 0x00 - 0xff 0x01 cell header used for in-stream ? programming cells. in-stream ? cell header byte 3 8012 [7:0] in-stream ? header [7:0] 0x00 - 0xff 0xf2 cell header used for in-stream ? programming cells. table 18 in-stream tm register table % discover/ identify 2 this command will generate an acknowledge reply cell containing 32 bytes of device specific data, which is stored in bytes 8 through 39 of the eeprom. reset 3 performs a reset on 77v011 device. no reply notification cell is returned acknowl edging t hat the reset com- mand has been completed. read registers 5 read from a consecutive number of registers. write registers 6 write to a consecutive number of registers. event notification 8 an unsolicited event notification cell indicating an event has taken place. the event can be either a phy inter- rupt or a address range error. table 19 in-stream tm programming message type indicator ! & @. 0 phy interrupt time out a phy interrupt was detected more than 25ms ago, but the phy interrupt bit of the status register has no t been cleared. 1 phy interrupt status a phy interrupt has been detected. 2 address range error time out an address range error was detected more than 25ms ago, but the address range error bit of the status register has not been cleared. 3 address range error status an address range error has been detected. 7:4 not used table 20 event notification table
30 of 43 march 15, 2001 IDT77V011 figure 20 general format in-stream tm programming cell format figure 21 valid header formats for in-stream tm programming cell figure 22 valid transaction field formats for in-st ream tm programming cell figure 23 valid message type format for in-stream tm programming cell byte 1 byte 5 byte 6 byte 7 byte 8 byte 9 byte 15 byte 16 byte 53 byte 52 byte 51 atm header message type transaction id device id message data and/or padding trailer 5348drw21 uni cell header (five byte field) 87654321 bit b y t e 1 2 3 4 5 gfc vpi vpi vci vci vci pt clp hec 5348drw22 nni cell header (five byte field) 87654321 bit b y t e 1 2 3 4 5 vpi vpi vci vci vci pt clp hec 5348drw23 command cell transaction id (two byte field) 87654321 bit b y t e 6 7 notification cell transaction id (two byte field) 87654321 bit b y t e 6 7 5348drw24 00000000 00000000 copied from command cell copied from command cell 87654321 bit b y t e 8 message type id acknowledge bit acknowledge request bit not used message type (one byte field) 5348drw25
31 of 43 march 15, 2001 IDT77V011 figure 24 valid device id field format for in-stream tm programming cell figure 25 valid message and/or data field format for in-st ream tm programming cell figure 26 valid trailer field format for in-stream tm programming cell device id (seven byte field) 87654321 bit b y t e 9 10 11 12 13 14 15 00000001 not used not used not used not used not used not used 5348drw26 87654321 bit b y t e 9 10 11 15 5348drw26a data from eeprom discovery/identify command cell device id (seven byte field) data from eeprom 12 13 14 read/write command cell message data and/or paddind field (36 byte field) 87654321 bit b y t e 16 17 18 19 20 51 5348drw27 number of valid bytes data and/or padding base address base address base address data and/or padding notification command cell message data and/or paddind field (36 byte field) 87654321 bit b y t e 16 17 18 51 5348drw28 data and/or padding data and/or padding event number event number discover/identify command cell message data and/or paddind field (36 byte field) 87654321 bit b y t e 16 40 41 51 5348drw29 data from eeprom reserved reserved data from eeprom trailer (two byte field) 87654321 bit b y t e 52 53 5348drw30 000000 crc10 crc10
32 of 43 march 15, 2001 IDT77V011 $% $% ! & ! $% ' ( ' notification mask 8008 0 phy interrupt mask 0 - 1 0 mask interrupt notification. "0" no event notification cell will be generated when a phy interrupt occurs, "1" generate event notification cell when a phy interrupt occurs. status 8009 0 phy interrupt 0 - 1 0 when a interrupt occurs on the phyint pin this bit will be set to a one. "0" no interrupt detected, "1" phy interrupt detected. timeout status 800a 0 phy interrupt status 0 - 1 0 indicates that a phy interrupt occurred more than 25ms ago, and the phy interrupt bit of the status register has not been cleared. this bit will return to zero once the interrupt is cleared. "0" no phy interrupt dete cted, "1" interrupt occurred more than 25ms ago and has not been cleared. table 21 interrupt register table +

+

+

+

there are two types of notification cells, event and reply, that can be generated by the 77v011. the 77v011 will generate an event notification cell if an interrupt is detected on the external phyint pin, or if an address range error is encountered. a second event notification cell will be generated if the interrupt is not cleared within 25ms of when it occurred. a dditi onal event notification cells will be generated every 12ms thereafter until the inter- rupt is cleared. a new event will not be r eported until the related interrupt has been cleared. it is up to the cpu to clear the interrupt, or to notify higher layers that an interrupt has occurred. the interrupts are cleared by writing a one to the phy interrupt or address range error bits in the status register. writing a one will clear the interrupt and reset the register bit to zero. the 77v011 will generate a reply no tificat ion cell if the acknowledge request bit is set to a one. reply notification cells enable the cpu to keep status of its command cells. " " " "

"
"
"
" when an interrupt occurs the status register will indicate where the interrupt occurred. the phy interrupt mask and rx address error bits of the no tification mask register determine if a event notification cell will be generated when an interrupt is detected. the 77v011 will not generate a event notification cell when an interrupt occurs if the register is set to the default of zero, and will generate a event notification cell if set to a one. the tx cell drop bit of the status register must be polled by the cpu to determine if it is set or not set. an e vent notification cell is not gener- ated when this bit is set, and no action needs to be taken by the cpu. however, the bit must be cleared, by writing a zero to it, in order to detect additional cells that have been dropped. the phy interrupt status and address error status bits of the timeout status register indicate that the interrupt occurred more than 25ms ago. this is a read only register used to verify that the interrupts are being cleared by the cpu. once an interrupt is detected the 77v011 will monitor the appropriate status register bit to determine if the inter- rupt is cleared. the 77v011 will generate a event notification cell, mask bit must be set to a one, if the interrupt is not cleared within 25ms of when the interrupt occurred and will set the timeout status bit. it will generate additi onal event notification cells on 12ms intervals, thereafter, until the interrupt is cleared. it is the cpu's responsibility to clear the interrupt and/or notify higher layers that an interrupt has been encoun- tered. the interrupt is cleared by the cpu writing a one to the appro- priate status register bit. writing a one will clear the interrupt and reset the register bit back to zero. see interrupt register table for description of interrupt registers.

the transmit and receive cell counters are always enabled. at reset the counters are set to zero and will increment by one each time a cell is received or transmitted over the utopia interface. the counter values are stored in the utopia tx and rx cell counter registers and can be read at any time. the counters will roll over once the maximum cell count is reached.

, , , , the 77v011 offers two external control pins, cntrl_a and cntrl_b, that can be connected to an external device for system design engineer usage. both of these signals are low after reset. there is also a register associated with each control pin signal, which is described in the misc. register table.
33 of 43 march 15, 2001 IDT77V011 $% 62@a8 ! 4 ! ( ' utopia rx cell counter byte 3 801b [7:0] rx cell counter [31:24] 0x00 counter for cells transferred on the receive utopia 2 bus. this counter will wrap around once the maximum cell count is reached. utopia rx cell counter byte 2 801c [7:0] rx cell counter [23:16] 0x00 counter for cells transferred on the receive utopia 2 bus. this counter will wrap around once the maximum cell count is reached. utopia rx cell counter byte 1 801d [7:0] rx cell counter [15:8] 0x00 counter for cells transferred on the receive utopia 2 bus. this counter will wrap around once the maximum cell count is reached. utopia rx cell counter byte 0 801e [7:0] rx cell counter [7:0] 0x00 counter for cells transferred on the receive utopia 2 bus. this counter will wrap around once the maximum cell count is reached. utopia tx cell counter byte 3 801f [7:0] tx cell counter [31:24] 0x00 counter for cells transferred on the transmit utopia 2 bus. this counter will wrap around once the maximum cell count is reached. utopia tx cell counter byte 2 8020 [7:0] tx cell counter [23:16] 0x00 counter for cells transferred on the transmit utopia 2 bus. this counter will wrap around once the maximum cell count is reached. utopia tx cell counter byte 1 8021 [7:0] tx cell counter [15:8] 0x00 counter for cells transferred on the transmit utopia 2 bus. this counter will wrap around once the maximum cell count is reached. utopia tx cell counter byte 0 8022 [7:0] tx cell counter [7:0] 0x00 counter for cells transferred on the transmit utopia 2 bus. this counter will wrap around once the maximum cell count is reached. table 22 cell counter register table $% $% ! & ! $% ' ( ' pin controls 801a 1 control a 0 - 1 0 stores condition of control a pin. "0" cntrl_a = "0", "1" cntrl_a = "1". 2 control b 0 - 1 0 stores condition of control b pin. "0" cntrl_b = "0", "1" cntrl_b = "1". table 23 misc.+ register table
t cyc sysclk cycle time 20 ? ns t ch sysclk high time 8 ? ns t cl sysclk low time 8 ? ns t ucyc utopia tclk/rclk cycle time 25 ? ns t uch utopia tclk/rclk high time 10 ? ns t ucl utopia tclk/rclk low time 10 ? ns t tov txdata, tenb, tsoc output valid from tclk 2 20 ns t uts tclav to tclk setup time 4 ? ns t uth tclav to tclk hold time 1 ? ns t rov renb output valid from rclk ? 20 ns t urs rxdata, rsoc, rclav to rclk setup time 10 ? ns t urh rxdata, rsoc, rclav to rclk hold time 1 ? ns table 24 ac electrical characteristics (industrial: vcc = 5v 10%, ta = -40 c the 85 c (part 1 of 3)
34 of 43 march 15, 2001 IDT77V011 t dcyc dpi dtxclk/drxclk cycle time 20 ? ns t dch dpi dtxclk/drxclk high time 8 ? ns t dcl dpi dtxclk/drxclk low time 8 ? ns t dts dtxfrm, dtxdata to dtclk setup time 4 ? ns t dth dtxfrm, dtxdata to dtclk hold time 2 ? ns t pdrd drxclk to drxdata(0-3), drxfrm propagation delay ? 10 ns t alpw ale pulse width 20 ? ns t alr system clock to read low propagation delay ? 20 ns t alw system clock to write low propagation delay ? 20 ns t rdpw read pulse width 80 ? ns t aal address to ale falling edge setup time 20 ? ns t ala address to ale falling edge hold time 10 ? ns t drs data to rising edge of read setup time 5 ? ns t drh data to rising edge of read hold time 1 ? ns t dws data to rising edge of write setup time 5 ? ns t dwh data to rising edge of write hold time 1 ? ns t wrpw write pulse width 40 ? ns t pints system clock to phyint setup time 10 ? ns t pinth system clock to phyint hold time 1 ? ns t aw ale falling edge to wr falling edge 25 ? ns t pale ale to system clock propagation delay ? 20 ns t pphy system clock to phycs propagation delay ? 20 ns t pphyr system clock to phyrst propagation delay ? 20 ns t prclk system clock to utopia receive clock propagation delay ? 20 ns t ptclk system clock to utopia transmit clock propagation delay ? 20 ns t pdrxclk system clock to dpi receive clock propagation delay ? 20 ns t pdtxclk system clock to dpi transmit clock propagation delay ? 20 ns t prled system clock to rxled propagation delay ? 20 ns t ptled system clock to txled propagation delay ? 20 ns t pcnta system clock to cont_a propagat ion delay ? 20 ns t pcntb system clock to cont_b propagat ion delay ? 20 ns t rstw sysrst pulse width 100 ? ns t ecyc eeclk cycle time 1000 ? ns t peclk sysclk to eeclk, eecs , eedout propagation delay ? 20 ns t sedi sysclk to eedin setup time ? 10 ns t hedi sysclk to eedin hold time 2 ? ns
table 24 ac electrical characteristics (industrial: vcc = 5v 10%, ta = -40 c the 85 c (part 2 of 3)
35 of 43 march 15, 2001 IDT77V011 figure 27 system clock timing waveform figure 28 system clock to utopia receive clock propagation delay figure 29 system clock to utopia transmit clock propagation delay t adrs addr to rd /ds falling edge setup time 10 ? ns t adrh addr to rd /ds rising edge hold time 4 ? ns t selrs sel to rd /ds falling edge setup time 5 ? ns t selrh sel to rd /ds rising edge hold time 0 ? ns t dariv data invalid/tri-state to rd /ds rising edge 15 ? ns t darv data valid to rdy /dtack falling edge ? 10 ns t rdyrv rdy /dtack valid to rd /ds falling edge ? 15 ns t rdyrt rdy /dtack tri-state to rd /ds rising edge 10 ? ns t rdpw rd /ds pulse width 50 ? ns t rdywv rdy /dtack to wr /rw falling edge ? 15 ns t rdywt rdy /dtack tri-state to wr /rw rising edge ? 10 ns t adws addr to wr /rw falling edge setup time 15 ? ns t selws sel to wr /rw falling edge setup time 5 ? ns t selwh sel to wr /rw rising edge hold time 0 ? ns t daws data to wr /rw rising edge setup time 15 ? ns t dawh addr, data to wr /rw rising edge hold time 4 ? ns t wrpw wr /rw pulse width 50 ? ns
table 24 ac electrical characteristics (industrial: vcc = 5v 10%, ta = -40 c the 85 c (part 3 of 3) sysclk 5348drw31 t cyc t ch t cl sysclk rclk tprclk 5348drw32 sysclk tclk tptclk 5348drw33
36 of 43 march 15, 2001 IDT77V011 figure 30 system clock to dpi receive clock propagation delay figure 31 system clock to dpi transmit clock propagation delay figure 32 utopia transmit timing waveform figure 33 utopia receive timing w aveform figure 34 dpi transmit timing waveform sysclk drxclk tpdrxclk 5348drw34 sysclk dtxclk tpdtxclk 5348drw35 tclk 5348drw36 tclav txdata(0-7), tenb ,tsoc t tov t uch t ucl t uts t uth t ucyc rclk 5348drw37 renb rxdata(0-7), rsoc, rclav t rov t urs t urh dtxclk 5348drw38 dtxfrm, dtxdata(0-3) t dth t dcyc t dts t dch t dcl
37 of 43 march 15, 2001 IDT77V011 figure 35 dpi receive timing w aveform figure 36 system clock to phyrst propagation delay figure 37 system clock to phyint propagation delay figure 38 sysrst timing waveform figure 39 eeprom timing waveform drxclk 5348drw39 drxfrm, drxdata(0-3) t pdrd sysclk phyrst 5348drw4 0 tpphyr sysclk phyint 5348drw4 1 tpinth tpints sysrst 5348drw4 2 trstw sysclk eeclk eecs eedi eedo 5348drw43 t peclk t sedi t hedi
38 of 43 march 15, 2001 IDT77V011 " " " "

$% 62@a8 ! 4 ! ( ' device id 8000 [7:0] device version number 0x10 this is the device version number. 77v011 = 0x10. configuration 1 8001 0 drop tx cell 0 "selects whether or not to drop cell with invalid subport address. "0" do not drop the cell, "1" drop the cell." 1 copy efci 0 "selects whether or not to or the efci bit of the cell header with the efci bit of the 4-byte tag area appended to the beg inning of the cell, and place the or ? ed efci bit in the cell header. this option is not valid when the tag is appended to the end of the cell. "0" do not or the efci bit to the 4-byte tag area, "1" or the efci bit to the 4-byte tag area." 2rx move pt/ clp 0 "selects whether or not to move the pt/clp fields from the cell header into the 4-byte tag area appended to the beginning of the cell. this option is not valid when the tag is appended to the end of the cell. "0" do not move the pt/clp to the 4-byte tag area, "1" move the pt/clp to the 4-byte tag area. " 3 tx move pt/clp 0 "selects whether or not to move the pt/clp fields from the 4-byte tag area appended to the beg inning of the cell into the cell header. this option is not valid when the tag is appended to the end of the cell. "0" do not move the pt/clp fields to the cell header, "1" move the pt/clp fields to the cell header." [7:4] not used configuration 2 8002 [1:0] stall tx 0x0 "selects whether or not to stall the pipeline if the phy transmit fifo is full. "0" drop the cell, "1" stall the pipeline i ndefinitely, "2" stall the pipeline for stall cycles." [6:2] max subports 0x1e indicates the maximum subport address value for the phy(s) c onnected to the transmit utopia ii interface. 7 not used configuration 3 8003 [7:0] stall tx cycles 0xff number of tclk cycles the interface has to stall the pipeline when the phy transmit fifo is full. this field is valid only if the stall pipeline for stall cycles option is selected. tx tag 8004 [2:0] tx tag size defined by pin number of bytes to remove from the atm cell in the transmit direction. valid values are from zero to four. 3 tx add hec defined by pin "add a hec placeholder in the transmit direction. "0" do not add a hec placeholder, "1" add a hec placeholder." 4 tx tag location defined by pin "tag location in transmit direction. "0" transmit tag is located at the begin- ning of the cell, "1" transmit tag is located at the end of the cell." [7:5] not used rx tag 8005 [2:0] rx tag size defined by pin number of bytes to add to atm cell in the receive direction. valid values are from zero to four. 3 rx remove hec defined by pin "remove hec byte from cell. "0" do not remove the hec byte from the cell, "1" remove the hec byte from the cell." 4 rx tag location defined by pin "tag location in receive direction. "0" receive tag is loc ated at the begin- ning of the cell, "1" receive tag is loc ated at the end of the cell." [7:5] not used table 25 internal register map (part 1 of 4)
39 of 43 march 15, 2001 IDT77V011 mode select 8006 0 dpi size defined by pin "selects the size of the dpi tx and rx data bus. "0" 4-bit dpi tx and rx data bus, "1" 8-bit dpi tx and rx data bus." 1 dpi mode defined by pin "selects drxclk direction. "0" switch mode (output), "1" normal mode (input)." 2 utopia 2 size defined by pin "selects the size of the utopia 2 tx and rx data bus. "0" 8-bit utopia 2 tx and rx data bus, "1" 16-bit utopia 2 tx and rx data bus." 3 utopia man- agement mode defined by pin "selects type of management interface to use. "0" utility bus style, "1" uto- pia 2 management style." 4 init from eeprom defined by pin "five byte write from eeprom to in-stream ? cell header and in-stream ? subport registers at reset. "0" do not write five byte value, "1" write five byte value to registers." [7:5] not used phy reset 8007 0 phy reset 0 "phy reset. "0" do not reset the phy, "1" reset the phy(phyrst signal will be asserted low for at least 16 sysclk cycles." [7:1] not used notification mask 8008 0 phy interrupt mask 0 "mask interrupt notification. "0" no event notification cell will be generated when a phy interrupt occurs, "1" generate event notification cell when a phy interrupt occurs." 1 rx address error 0 "mask address range error notification. "0" no event notification cell will be generated when a rx out of range address error occurs, "1" generate event notification cell when a rx out of range address error occurs." [7:2] not used status 8009 0 phy interrupt 0 "when a phy interrupt occurs on the external phy interrupt pin this bit will be set high. "0" no interrupt detected, "1" phy interrupt detected." 1 address range error 0 "address range error indication when an address range error occurs. "0" no address range error detected, "1" address range error has been detected." 2 tx cell dropped 0 "indicates if any cells have been dropped at the transmit utopia interface. this is a status indicator for the stall tx bit of the configuration 2 register "0" no cells have been dropped, "1" a cell was dropped because the phy did not respond." [7:3] not used timeout status 800a 0 phy interrupt status 0 "indicates that a phy interrupt occurred more than 25ms ago, and the phy interrupt bit of the status register has not been cleared. this bit will return to zero once the interrupt is cleared. "0" no phy interrupt detected, "1" inter- rupt occurred more than 25ms ago and has not been c leared." 1 address error status 0 "indicates that a address error occurred more than 25ms ago, and address range error bit of the status register has not been cleared. this bit will return to zero once the interrupt is cleared. "0" no address r ange errors detected, "1" address range error occurred more than 25ms ago and has not been cleared." [7:2] not used $% 62@a8 ! 4 ! ( ' table 25 internal register map (part 2 of 4)
40 of 43 march 15, 2001 IDT77V011 rx out of range subport 800b [4:0] rx out of range subport 0x00 the subport address of a cell containing an invalid cell header. [7:5] not used rx out of range address mask byte 2 801c [7:0] address mask register [23:16] 0x00 value used to validate cells on the rx ut opia interface. rx out of range address mask byte 1 800d [7:0] address mask register [15:8] 0x00 value used to validate cells on the rx ut opia interface. rx out of range address mask byte 0 800e [7:0] address mask register [7:0] 0x00 value used to validate cells on the rx ut opia interface. in-stream ? cell header byte 3 800f [7:0] in-stream ? header [31:24] 0x00 cell header used for in-stream ? programming cells. in-stream ? cell header byte 2 8010 [7:0] in-stream ? header [23:16] 0x00 cell header used for in-stream ? programming cells. in-stream ? cell header byte 1 8011 [7:0] in-stream ? header [15:8] 0x01 cell header used for in-stream ? programming cells. in-stream ? cell header byte 0 8012 [7:0] in-stream ? header [7:0] 0xf2 cell header used for in-stream ? programming cells. subport configuration 1 8013 [4:0] in-stream ? subport 0x00 subport address used to filter in-stream ? programming cells. [7:5] tx subport width 0x5 programs how many bits will be used for subport addressing in the transmit direction. modify tx subport 8014 [4:0] new subport 0x00 new value used to replace s ubport address in outgoing cells. this value will only be used if the replace subport bit of the modify tx subport register is set to a one. 5 replace subport 0 "indicates whether or not to replace the subport address in transmit cells. "0" do not replace the subport address, "1" replace the subport address with the value in the new subport bits of the modify tx subport register." [7:6] not used tx subport position 8015 [2:0] tx byte location defined by pin indicates what byte of the transmit cell header the s ubport starts in. the subport address can cross the byte bo undary. [5:3] tx bit location 0x5 indicates what bit of the byte defined by the tx byte location bits of the tx subport position register the msb of the transmit su bport address starts. the subport address can cross the byte boundary. [7:6] not used tag byte 3 8016 [7:0] tag [31:24] 0x00 tag added to cell. tag byte 2 8017 [7:0] tag [23:16] 0x00 tag added to cell. tag byte 1 8018 [7:0] tag [17:8] 0x00 tag added to cell. tag byte 0 8019 [7:0] tag [7:0] 0x00 tag added to cell. $% 62@a8 ! 4 ! ( ' table 25 internal register map (part 3 of 4)
41 of 43 march 15, 2001 IDT77V011 pin controls 801a 0 override pin configuration 0 "enables writing to pin configurable registers during normal operation. "0" pin configurable registers are read only, "1" pin configurable registers are read/write registers." 1 control a 0 "stores condition of control a pin. "0" cntrl_a = "0", "1" cntrl_a = "1"." 2 control b 0 "stores condition of control b pin. "0" cntrl_b = "0", "1" cntrl_b = "1"." 3 eeprom mux select 0 "indicates if the eeprom interface will be connected to the internal logic or the eeprom registers. "0" connected to internal logic, "1" connected to eeprom registers." 4 eeprom clock out 0 "eeprom clock when eeprom interface is connected to the eeprom registers. "0" clock low, "1" clock high." 5 eeprom chip select 0 "eeprom chip select when eeprom interface is c onnec ted to the eeprom registers. "0" eeprom interface is selected, "1" eeprom inter- face is not selected." 6 eeprom out 0 eeprom serial output when eeprom interface is connected to the eeprom registers. 7 eeprom in 0 eeprom serial input when eeprom interface is connected to the eeprom registers. utopia rx cell counter byte 3 801b [7:0] rx cell counter [31:24] 0x00 counter for cells transferred on the receive ut opia 2 bus. this c ounter will wrap around once the maximum cell c ount is reac hed. utopia rx cell counter byte 2 801c [7:0] rx cell counter [23:16] 0x00 counter for cells transferred on the receive ut opia 2 bus. this c ounter will wrap around once the maximum cell c ount is reac hed. utopia rx cell counter byte 1 801d [7:0] rx cell counter [15:8] 0x00 counter for cells transferred on the receive ut opia 2 bus. this c ounter will wrap around once the maximum cell c ount is reac hed. utopia rx cell counter byte 0 801e [7:0] rx cell counter [7:0] 0x00 counter for cells transferred on the receive ut opia 2 bus. this c ounter will wrap around once the maximum cell c ount is reac hed. utopia tx cell counter byte 3 801f [7:0] tx cell counter [31:24] 0x00 counter for cells transferred on the transmit utopia 2 bus. this counter will wrap around once the maximum cell c ount is reac hed. utopia tx cell counter byte 2 8020 [7:0] tx cell counter [23:16] 0x00 counter for cells transferred on the transmit utopia 2 bus. this counter will wrap around once the maximum cell c ount is reac hed. utopia tx cell counter byte 1 8021 [7:0] tx cell counter [15:8] 0x00 counter for cells transferred on the transmit utopia 2 bus. this counter will wrap around once the maximum cell c ount is reac hed. utopia tx cell counter byte 0 8022 [7:0] tx cell counter [7:0] 0x00 counter for cells transferred on the transmit utopia 2 bus. this counter will wrap around once the maximum cell c ount is reac hed. subport configuration 2 8023 [2:0] rx subport width 0x5 programs how many bits will be used for s ubport addressing in the receive direction. [7:3] not used rx subport position 8024 [2:0] rx byte location defined by pin indicates what byte of the receive cell header the s ubport starts in. the sub- port address can cross the byte boundary. [5:3] rx bit location 0x5 indicates what bit of the byte defined by the rx byte location bits of the rx subport position register the msb of the receive s ubport address starts. the subport address can cross the byte boundary. [7:6] not used $% 62@a8 ! 4 ! ( ' table 25 internal register map (part 4 of 4)
42 of 43 march 15, 2001 IDT77V011 " " " "

plastic qfp 144pin body size 20 x 20 x 1.4mm

1. for reference min norm max min norm max e 19.9 20 20.1 (0.784) (0.787) (0.791) d 19.9 20 20.1 (0.784) (0.787) (0.791) a 1.7 (0.066) a1 0.1 (0.004) a2 1.3 1.4 1.5 (0.052) (0.055) (0.059) f0.5 (0.020) b 0.15 0.2 0.3 (0.006) (0.008) (0.011) c 0.1 0.125 0.175 (0.004) (0.005) (0.006) 0 o 10 o (0 o )(10 o ) l 0.3 0.5 0.7 (0.012) (0.020) (0.027) l1 1 (0.039) l2 0.5 (0.020) he 21.6 22 22.4 (0.851) (0.866) (0.881) hd 21.6 22 22.4 (0.851) (0.866) (0.881) 2 12 o (12 o ) 3 12 o (12 o ) r0.2 (0.008) r1 0.2 (0.008) 108 73 h d d e 37 72 36 1 144 109 index b f h e a 2 a 1 a m a x r 1 r c l 2 l l 1 2 3 5348drw4 4
43 of 43 march 15, 2001 IDT77V011 corporate headquarters 2975 stender way santa clara, ca 95054 for sales: 800-345-7015 or 408-727-6116 f ax: 408 - 33 0 - 17 48 www.idt.com for tech support: email: sarhelp@idt.com phone: 408 - 49 2 - 8 2 0 8 the idt logo is a registered trademark of integrated device technology, inc.

" " " "

-
-
-
-
' '' ' 9/28/99 initial public release 01/17/00 corrected package type from dx to da in ordering information, corrected typo sclk to sysclk in ac electrical characteristics, corrected sales and tech support phone numbers. 02/03/00 fixed typos in in-stream ? text. 03/03/00 deleted commercial temperature range and ordering information, changed bandwidth chart to refl ect maximum values, updated utilit y bus write timing. 05/15/00 corrected table 5348 tbl15 8-bit utopia to 8-bit dpi conversion. 09/12/00 corrected in-stream ? data field description and drawing for notification cells, moved copy efci description from receive tag to transmit tag section. 10/01/00 changed default in-stream ? header value from 0x1f0 to 0x1f2. corrected register descriptions and text for copy efci, rx move pt/clp, and tx move pt/clp. 1218/00 added draw ing 5248drw26a and corrected text for discover/i dentify c ommand. changed in-stream ? text for read/ write command from 32- bytes to 31-bytes. corrected register address map drawing 5348drw18. added subport text to in-stream ? header detection text. changed default tag byte 0 and 1 to 0x00. removed tag byte 0, 1, 2, and 3 from table 5348tbl28. c hanged from pre liminary to final. 3/15/01 in pin configuration diagram, ctrl_b changed from pin 53 to pin 52 and ctrl_a ch anged from pin 52 to pin 53. in ac electrical characteris- tics table, changed t uth from 10ns to 1ns. a power 999 speed a package a process/ temperature range (blank) industrial da pqfp (144-pin) 155 llowpower xxxxx device type data path interface (dpi) to utopia level 1 header translation device 77v011 idt 5348drw45 4-bit port bandwidth in mbps

▲Up To Search▲

Price & Availability of IDT77V011

	To Download IDT77V011 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .